[Mesa-dev] separate depth and stencil buffers in gallium
keith.whitwell at gmail.com
Wed Sep 22 02:50:50 PDT 2010
On Wed, Sep 22, 2010 at 10:30 AM, Dave Airlie <airlied at gmail.com> wrote:
> So Evergreen hardware appears to have only completely separate depth
> and stencil buffers and doesn't natively support a combnined DS buffer
> from what I can see. I'm awaiting clarification from AMD.
> Now gallium and st/mesa seem to be quite dedicated to the whole
> combined DS cause.
What formats exactly does it support?
It's interesting because DX10 (and presumably 11) always talk about
combined buffers - but the abstraction is such (with staging
resources, no direct mapping of the buffers, etc) that there's nothing
which constrains the layout to be an interleaved depth+stencil. IE.
you could quite happily allocate the combined depth/stencil as a
planar depth buffer and a separate planar stencil buffer - both hidden
behind the same resource handle.
I would have hoped we'd have the same flexibility in gallium -
basically that nobody should be able to tell whether depth & stencil
are swizzled together or separate.
The obvious case where the app & state tracker might be alerted to
your unusual layout is in transfers. An interim solution would be to
swizzle/unswizzle depth buffer transfer data (or organize for the card
to do so for you).
> I'm mainly posting just wondering if anyone else has considered this
> or any other hardware this might be useful for exists, or if anyone
> can speak to the pitfalls I'll face.
> I've got some initial done in 30 mins hacks
I'll take a look.
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