[Mesa-dev] Mesa (master): i965: clear global offset to zero in m0.2 for VS DP read.

[Zou, Nanhai]

That is a duplicated fix as commit
9d60a7ce08a67eb8b79c60f829d090ba4a37ed7e.
I have reverted the patch.
Please pick 9d60a7ce08a67eb8b79c60f829d090ba4a37ed7e.
Thanks
Zou Nanhai
>>-----Original Message-----
>>From: Ian Romanick [mailto:idr at freedesktop.org]
>>Sent: 2011年4月12日 0:20
>>To: Eric Anholt
>>Cc: Zou, Nanhai; mesa-dev at lists.freedesktop.org
>>Subject: Re: [Mesa-dev] Mesa (master): i965: clear global offset to zero in
>>m0.2 for VS DP read.
>>
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>>On 04/11/2011 08:31 AM, Eric Anholt wrote:
>>> On Mon, 11 Apr 2011 17:16:34 +0800, "Zou, Nanhai" <nanhai.zou at intel.com>
>>wrote:
>>>> In fact this is not zero at multi vs thread cases on GT1, it will trigger
>>DP read error when multi vs thread is enabled.
>>>>
>>>> I can not find where in spec says this payload M0.2 is reserved as zero,
>>>
>>> g0.2 is delivered as 0.  See vol2a.03: Thread Payload.  We rely on that
>>> all over the place, not just in the VS.
>>>
>>> In brw_dp_read_4_vs, before your change, m0.2 was already getting set.
>>>
>>> In brw_dp_read_4_vs_relative, before your change, m0 was loaded with g0
>>> through gen6_resolve_implied_move(p, &src, 0).
>>>
>>> In both cases, your change is dead instructions as far as I can see.
>>
>>It seems like it should be, but this change makes several previously
>>failing tests pass on GT2 and GT1.  In particular, some tests that use
>>matrices for vertex inputs used to fail in single- or multi-threaded,
>>but they now pass.
>>
>>That said, I share Eric's concerns, and I want to understand why this
>>change works before cherry picking it to stable.
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