[Mesa-dev] [PATCH 7/8] i965 gen6+: Make intel_batchbuffer_emit_mi_flush() actually flush.
eric at anholt.net
Sat Dec 17 11:53:30 PST 2011
On Tue, 13 Dec 2011 15:35:20 -0800, Paul Berry <stereotype441 at gmail.com> wrote:
> Previous to this patch, the function intel_batchbuffer_emit_mi_flush()
> was a bit of a misnomer. On Gen4+, when not using the blit engine, it
> didn't actually flush the pipeline--it simply generated a
> _3DSTATE_PIPE_CONTROL command with the necessary bits set to flush GPU
> caches. This was usually sufficient, since in most situations where
> intel_batchbuffer_emit_mi_flush() wass called, all we really care
> about was ensuring cache coherency.
I think I've validated that the set of workarounds doesn't change when
adding the CS stall bit.
Reviewed-by: Eric Anholt <eric at anholt.net>
-------------- next part --------------
A non-text attachment was scrubbed...
Name: not available
Size: 197 bytes
Desc: not available
More information about the mesa-dev