[Mesa-dev] [PATCH 3/7] i965/gen7: Add register definitions for GL_EXT_transform_feedback.
Eric Anholt
eric at anholt.net
Thu Dec 22 16:54:46 PST 2011
Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>
---
src/mesa/drivers/dri/i965/brw_defines.h | 76 ++++++++++++++++++++++++++++++-
src/mesa/drivers/dri/intel/intel_reg.h | 15 ++++++
2 files changed, 89 insertions(+), 2 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_defines.h b/src/mesa/drivers/dri/i965/brw_defines.h
index 4edfaf7..4bb7f00 100644
--- a/src/mesa/drivers/dri/i965/brw_defines.h
+++ b/src/mesa/drivers/dri/i965/brw_defines.h
@@ -1307,6 +1307,42 @@ enum brw_wm_barycentric_interp_mode {
#define _3DSTATE_CONSTANT_HS 0x7819 /* GEN7+ */
#define _3DSTATE_CONSTANT_DS 0x781A /* GEN7+ */
+#define _3DSTATE_STREAMOUT 0x781e /* GEN7+ */
+/* DW1 */
+# define SO_FUNCTION_ENABLE (1 << 31)
+# define SO_RENDERING_DISABLE (1 << 30)
+/* This selects which incoming rendering stream goes down the pipeline. The
+ * rendering stream is 0 if not defined by special cases in the GS state.
+ */
+# define SO_RENDER_STREAM_SELECT_SHIFT 27
+# define SO_RENDER_STREAM_SELECT_MASK INTEL_MASK(28, 27)
+/* Controls reordering of TRISTRIP_* elements in stream output (not rendering).
+ */
+# define SO_REORDER_TRAILING (1 << 26)
+/* Controls SO_NUM_PRIMS_WRITTEN_* and SO_PRIM_STORAGE_* */
+# define SO_STATISTICS_ENABLE (1 << 25)
+# define SO_BUFFER_ENABLE_3 (1 << 11)
+# define SO_BUFFER_ENABLE_2 (1 << 10)
+# define SO_BUFFER_ENABLE_1 (1 << 9)
+# define SO_BUFFER_ENABLE_0 (1 << 8)
+/* DW2 */
+# define SO_STREAM_3_VERTEX_READ_OFFSET_SHIFT 29
+# define SO_STREAM_3_VERTEX_READ_OFFSET_MASK INTEL_MASK(29, 29)
+# define SO_STREAM_3_VERTEX_READ_LENGTH_SHIFT 24
+# define SO_STREAM_3_VERTEX_READ_LENGTH_MASK INTEL_MASK(28, 24)
+# define SO_STREAM_2_VERTEX_READ_OFFSET_SHIFT 21
+# define SO_STREAM_2_VERTEX_READ_OFFSET_MASK INTEL_MASK(21, 21)
+# define SO_STREAM_2_VERTEX_READ_LENGTH_SHIFT 16
+# define SO_STREAM_2_VERTEX_READ_LENGTH_MASK INTEL_MASK(20, 16)
+# define SO_STREAM_1_VERTEX_READ_OFFSET_SHIFT 13
+# define SO_STREAM_1_VERTEX_READ_OFFSET_MASK INTEL_MASK(13, 13)
+# define SO_STREAM_1_VERTEX_READ_LENGTH_SHIFT 8
+# define SO_STREAM_1_VERTEX_READ_LENGTH_MASK INTEL_MASK(12, 8)
+# define SO_STREAM_0_VERTEX_READ_OFFSET_SHIFT 5
+# define SO_STREAM_0_VERTEX_READ_OFFSET_MASK INTEL_MASK(5, 5)
+# define SO_STREAM_0_VERTEX_READ_LENGTH_SHIFT 0
+# define SO_STREAM_0_VERTEX_READ_LENGTH_MASK INTEL_MASK(4, 0)
+
/* 3DSTATE_WM for Gen7 */
/* DW1 */
# define GEN7_WM_STATISTICS_ENABLE (1 << 31)
@@ -1373,8 +1409,6 @@ enum brw_wm_barycentric_interp_mode {
/* DW6: kernel 1 pointer */
/* DW7: kernel 2 pointer */
-#define _3DSTATE_STREAMOUT 0x781e /* GEN7+ */
-
#define _3DSTATE_SAMPLE_MASK 0x7818 /* GEN6+ */
#define _3DSTATE_DRAWING_RECTANGLE 0x7900
@@ -1414,6 +1448,44 @@ enum brw_wm_barycentric_interp_mode {
# define DEPTH_CLEAR_VALID (1 << 15)
/* DW1: depth clear value */
+#define _3DSTATE_SO_DECL_LIST 0x7917 /* GEN7+ */
+/* DW1 */
+# define SO_STREAM_TO_BUFFER_SELECTS_3_SHIFT 12
+# define SO_STREAM_TO_BUFFER_SELECTS_3_MASK INTEL_MASK(15, 12)
+# define SO_STREAM_TO_BUFFER_SELECTS_2_SHIFT 8
+# define SO_STREAM_TO_BUFFER_SELECTS_2_MASK INTEL_MASK(11, 8)
+# define SO_STREAM_TO_BUFFER_SELECTS_1_SHIFT 4
+# define SO_STREAM_TO_BUFFER_SELECTS_1_MASK INTEL_MASK(7, 4)
+# define SO_STREAM_TO_BUFFER_SELECTS_0_SHIFT 0
+# define SO_STREAM_TO_BUFFER_SELECTS_0_MASK INTEL_MASK(3, 0)
+/* DW2 */
+# define SO_NUM_ENTRIES_3_SHIFT 24
+# define SO_NUM_ENTRIES_3_MASK INTEL_MASK(31, 24)
+# define SO_NUM_ENTRIES_2_SHIFT 16
+# define SO_NUM_ENTRIES_2_MASK INTEL_MASK(23, 16)
+# define SO_NUM_ENTRIES_1_SHIFT 8
+# define SO_NUM_ENTRIES_1_MASK INTEL_MASK(15, 8)
+# define SO_NUM_ENTRIES_0_SHIFT 0
+# define SO_NUM_ENTRIES_0_MASK INTEL_MASK(7, 0)
+
+/* SO_DECL DW0 */
+# define SO_DECL_OUTPUT_BUFFER_SLOT_SHIFT 12
+# define SO_DECL_OUTPUT_BUFFER_SLOT_MASK INTEL_MASK(13, 12)
+# define SO_DECL_HOLE_FLAG (1 << 11)
+# define SO_DECL_REGISTER_INDEX_SHIFT 4
+# define SO_DECL_REGISTER_INDEX_MASK INTEL_MASK(9, 4)
+# define SO_DECL_COMPONENT_MASK_SHIFT 0
+# define SO_DECL_COMPONENT_MASK_MASK INTEL_MASK(3, 0)
+
+#define _3DSTATE_SO_BUFFER 0x7918 /* GEN7+ */
+/* DW1 */
+# define SO_BUFFER_INDEX_SHIFT 29
+# define SO_BUFFER_INDEX_MASK INTEL_MASK(30, 29)
+# define SO_BUFFER_PITCH_SHIFT 0
+# define SO_BUFFER_PITCH_MASK INTEL_MASK(11, 0)
+/* DW2: start address */
+/* DW3: end address. */
+
#define CMD_PIPE_CONTROL 0x7a00
#define CMD_MI_FLUSH 0x0200
diff --git a/src/mesa/drivers/dri/intel/intel_reg.h b/src/mesa/drivers/dri/intel/intel_reg.h
index a98a669..e2a6ee2 100644
--- a/src/mesa/drivers/dri/intel/intel_reg.h
+++ b/src/mesa/drivers/dri/intel/intel_reg.h
@@ -44,6 +44,9 @@
#define MI_WAIT_FOR_PLANE_B_FLIP (1<<6)
#define MI_WAIT_FOR_PLANE_A_FLIP (1<<2)
+#define MI_STORE_REGISTER_MEM (CMD_MI | (0x24 << 23))
+# define MI_STORE_REGISTER_MEM_USE_GGTT (1 << 22)
+
/* p189 */
#define _3DSTATE_LOAD_STATE_IMMEDIATE_1 (CMD_3D | (0x1d<<24) | (0x04<<16))
#define I1_LOAD_S(n) (1<<(4+n))
@@ -260,3 +263,15 @@
#define FENCE_LINEAR 0
#define FENCE_XMAJOR 1
#define FENCE_YMAJOR 2
+
+#define SO_NUM_PRIM_STORAGE_NEEDED 0x2280
+#define SO_PRIM_STORAGE_NEEDED0_IVB 0x5240
+#define SO_PRIM_STORAGE_NEEDED1_IVB 0x5248
+#define SO_PRIM_STORAGE_NEEDED2_IVB 0x5250
+#define SO_PRIM_STORAGE_NEEDED3_IVB 0x5258
+
+#define SO_NUM_PRIMS_WRITTEN 0x2288
+#define SO_NUM_PRIMS_WRITTEN0_IVB 0x5200
+#define SO_NUM_PRIMS_WRITTEN1_IVB 0x5208
+#define SO_NUM_PRIMS_WRITTEN2_IVB 0x5210
+#define SO_NUM_PRIMS_WRITTEN3_IVB 0x5218
--
1.7.7.3
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