[Mesa-dev] [PATCH 06/10] intel: Make gl_program::InputsRead 64 bits.
Mathias Fröhlich
Mathias.Froehlich at gmx.net
Fri Nov 11 09:09:56 PST 2011
---
src/mesa/drivers/dri/i915/i915_fragprog.c | 4 ++--
src/mesa/drivers/dri/i965/brw_context.h | 2 +-
src/mesa/drivers/dri/i965/brw_draw_upload.c | 6 +++---
src/mesa/drivers/dri/i965/brw_vs.c | 4 ++--
src/mesa/drivers/dri/i965/brw_vs_constval.c | 2 +-
src/mesa/drivers/dri/i965/brw_vs_emit.c | 4 ++--
src/mesa/drivers/dri/i965/gen6_wm_state.c | 2 +-
src/mesa/drivers/dri/i965/gen7_wm_state.c | 2 +-
8 files changed, 13 insertions(+), 13 deletions(-)
diff --git a/src/mesa/drivers/dri/i915/i915_fragprog.c
b/src/mesa/drivers/dri/i915/i915_fragprog.c
index 063e155..4f016a3 100644
--- a/src/mesa/drivers/dri/i915/i915_fragprog.c
+++ b/src/mesa/drivers/dri/i915/i915_fragprog.c
@@ -1148,7 +1148,7 @@ fixup_depth_write(struct i915_fragment_program *p)
static void
check_wpos(struct i915_fragment_program *p)
{
- GLuint inputs = p->FragProg.Base.InputsRead;
+ GLbitfield64 inputs = p->FragProg.Base.InputsRead;
GLint i;
p->wpos_tex = -1;
@@ -1337,7 +1337,7 @@ i915ValidateFragmentProgram(struct i915_context *i915)
struct i915_fragment_program *p =
(struct i915_fragment_program *) ctx->FragmentProgram._Current;
- const GLuint inputsRead = p->FragProg.Base.InputsRead;
+ const GLbitfield64 inputsRead = p->FragProg.Base.InputsRead;
GLuint s4 = i915->state.Ctx[I915_CTXREG_LIS4] & ~S4_VFMT_MASK;
GLuint s2 = S2_TEXCOORD_NONE;
int i, offset = 0;
diff --git a/src/mesa/drivers/dri/i965/brw_context.h
b/src/mesa/drivers/dri/i965/brw_context.h
index fb03208..339d410 100644
--- a/src/mesa/drivers/dri/i965/brw_context.h
+++ b/src/mesa/drivers/dri/i965/brw_context.h
@@ -377,7 +377,7 @@ struct brw_vs_prog_data {
GLuint nr_pull_params; /**< number of dwords referenced by pull_param[] */
GLuint total_scratch;
- GLuint inputs_read;
+ GLbitfield64 inputs_read;
/* Used for calculating urb partitions:
*/
diff --git a/src/mesa/drivers/dri/i965/brw_draw_upload.c
b/src/mesa/drivers/dri/i965/brw_draw_upload.c
index db0cb18..872869c 100644
--- a/src/mesa/drivers/dri/i965/brw_draw_upload.c
+++ b/src/mesa/drivers/dri/i965/brw_draw_upload.c
@@ -355,7 +355,7 @@ static void brw_prepare_vertices(struct brw_context *brw)
struct gl_context *ctx = &brw->intel.ctx;
struct intel_context *intel = intel_context(ctx);
/* CACHE_NEW_VS_PROG */
- GLbitfield vs_inputs = brw->vs.prog_data->inputs_read;
+ GLbitfield64 vs_inputs = brw->vs.prog_data->inputs_read;
const unsigned char *ptr = NULL;
GLuint interleaved = 0, total_size = 0;
unsigned int min_index = brw->vb.min_index;
@@ -373,10 +373,10 @@ static void brw_prepare_vertices(struct brw_context
*brw)
/* Accumulate the list of enabled arrays. */
brw->vb.nr_enabled = 0;
while (vs_inputs) {
- GLuint i = ffs(vs_inputs) - 1;
+ GLuint i = _mesa_ffsll(vs_inputs) - 1;
struct brw_vertex_element *input = &brw->vb.inputs[i];
- vs_inputs &= ~(1 << i);
+ vs_inputs &= ~BITFIELD64_BIT(i);
if (input->glarray->Size && get_size(input->glarray->Type))
brw->vb.enabled[brw->vb.nr_enabled++] = input;
}
diff --git a/src/mesa/drivers/dri/i965/brw_vs.c
b/src/mesa/drivers/dri/i965/brw_vs.c
index 967f82e..6f9fd6a 100644
--- a/src/mesa/drivers/dri/i965/brw_vs.c
+++ b/src/mesa/drivers/dri/i965/brw_vs.c
@@ -207,7 +207,7 @@ do_vs_prog(struct brw_context *brw,
if (c.key.copy_edgeflag) {
c.prog_data.outputs_written |= BITFIELD64_BIT(VERT_RESULT_EDGE);
- c.prog_data.inputs_read |= 1<<VERT_ATTRIB_EDGEFLAG;
+ c.prog_data.inputs_read |= BITFIELD64_BIT(VERT_ATTRIB_EDGEFLAG);
}
/* Put dummy slots into the VUE for the SF to put the replaced
@@ -318,7 +318,7 @@ static void brw_upload_vs_prog(struct brw_context *brw)
/* BRW_NEW_VERTICES */
for (i = 0; i < VERT_ATTRIB_MAX; i++) {
- if (vp->program.Base.InputsRead & (1 << i) &&
+ if (vp->program.Base.InputsRead & BITFIELD64_BIT(i) &&
brw->vb.inputs[i].glarray->Type == GL_FIXED) {
key.gl_fixed_input_size[i] = brw->vb.inputs[i].glarray->Size;
}
diff --git a/src/mesa/drivers/dri/i965/brw_vs_constval.c
b/src/mesa/drivers/dri/i965/brw_vs_constval.c
index 8b7993a..9ce5ab3 100644
--- a/src/mesa/drivers/dri/i965/brw_vs_constval.c
+++ b/src/mesa/drivers/dri/i965/brw_vs_constval.c
@@ -202,7 +202,7 @@ static void calc_wm_input_sizes( struct brw_context *brw )
t.twoside = 1;
for (i = 0; i < VERT_ATTRIB_MAX; i++)
- if (vp->program.Base.InputsRead & (1<<i))
+ if (vp->program.Base.InputsRead & BITFIELD64_BIT(i))
set_active_component(&t, PROGRAM_INPUT, i,
szflag[get_input_size(brw, i)]);
diff --git a/src/mesa/drivers/dri/i965/brw_vs_emit.c
b/src/mesa/drivers/dri/i965/brw_vs_emit.c
index e39b3dd..bcaef04 100644
--- a/src/mesa/drivers/dri/i965/brw_vs_emit.c
+++ b/src/mesa/drivers/dri/i965/brw_vs_emit.c
@@ -311,7 +311,7 @@ static void brw_vs_alloc_regs( struct brw_vs_compile *c )
*/
c->nr_inputs = 0;
for (i = 0; i < VERT_ATTRIB_MAX; i++) {
- if (c->prog_data.inputs_read & (1 << i)) {
+ if (c->prog_data.inputs_read & BITFIELD64_BIT(i)) {
c->nr_inputs++;
c->regs[PROGRAM_INPUT][i] = brw_vec8_grf(reg, 0);
reg++;
@@ -1820,7 +1820,7 @@ brw_vs_rescale_gl_fixed(struct brw_vs_compile *c)
int i;
for (i = 0; i < VERT_ATTRIB_MAX; i++) {
- if (!(c->prog_data.inputs_read & (1 << i)))
+ if (!(c->prog_data.inputs_read & BITFIELD64_BIT(i)))
continue;
if (c->key.gl_fixed_input_size[i] != 0) {
diff --git a/src/mesa/drivers/dri/i965/gen6_wm_state.c
b/src/mesa/drivers/dri/i965/gen6_wm_state.c
index 271a9ae..9981a01 100644
--- a/src/mesa/drivers/dri/i965/gen6_wm_state.c
+++ b/src/mesa/drivers/dri/i965/gen6_wm_state.c
@@ -167,7 +167,7 @@ upload_wm_state(struct brw_context *brw)
dw5 |= GEN6_WM_POLYGON_STIPPLE_ENABLE;
/* BRW_NEW_FRAGMENT_PROGRAM */
- if (fp->program.Base.InputsRead & (1 << FRAG_ATTRIB_WPOS))
+ if (fp->program.Base.InputsRead & BITFIELD64_BIT(FRAG_ATTRIB_WPOS))
dw5 |= GEN6_WM_USES_SOURCE_DEPTH | GEN6_WM_USES_SOURCE_W;
if (fp->program.Base.OutputsWritten & BITFIELD64_BIT(FRAG_RESULT_DEPTH))
dw5 |= GEN6_WM_COMPUTED_DEPTH;
diff --git a/src/mesa/drivers/dri/i965/gen7_wm_state.c
b/src/mesa/drivers/dri/i965/gen7_wm_state.c
index f38d2f1..3775301 100644
--- a/src/mesa/drivers/dri/i965/gen7_wm_state.c
+++ b/src/mesa/drivers/dri/i965/gen7_wm_state.c
@@ -58,7 +58,7 @@ upload_wm_state(struct brw_context *brw)
dw1 |= GEN7_WM_POLYGON_STIPPLE_ENABLE;
/* BRW_NEW_FRAGMENT_PROGRAM */
- if (fp->program.Base.InputsRead & (1 << FRAG_ATTRIB_WPOS))
+ if (fp->program.Base.InputsRead & BITFIELD64_BIT(FRAG_ATTRIB_WPOS))
dw1 |= GEN7_WM_USES_SOURCE_DEPTH | GEN7_WM_USES_SOURCE_W;
if (fp->program.Base.OutputsWritten & BITFIELD64_BIT(FRAG_RESULT_DEPTH)) {
writes_depth = true;
--
1.7.4.4
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