[Mesa-dev] [PATCH 1/3] gallium: add PIPE_CAP_SHADER_OUTPUT_READ

[Vadim Girlin]

It's intended to indicate whether the driver/hardware supports reading
of the values written into shader outputs.

Also remove assert to allow using TGSI_FILE_OUTPUT registers
in the ureg_emit_src.

Signed-off-by: Vadim Girlin <vadimgirlin at gmail.com>
---
 src/gallium/auxiliary/tgsi/tgsi_ureg.c |    1 -
 src/gallium/include/pipe/p_defines.h   |    3 ++-
 2 files changed, 2 insertions(+), 2 deletions(-)

diff --git a/src/gallium/auxiliary/tgsi/tgsi_ureg.c b/src/gallium/auxiliary/tgsi/tgsi_ureg.c
index cada435..cd445a6 100644
--- a/src/gallium/auxiliary/tgsi/tgsi_ureg.c
+++ b/src/gallium/auxiliary/tgsi/tgsi_ureg.c
@@ -799,7 +799,6 @@ ureg_emit_src( struct ureg_program *ureg,
    unsigned n = 0;
 
    assert(src.File != TGSI_FILE_NULL);
-   assert(src.File != TGSI_FILE_OUTPUT);
    assert(src.File < TGSI_FILE_COUNT);
    
    out[n].value = 0;
diff --git a/src/gallium/include/pipe/p_defines.h b/src/gallium/include/pipe/p_defines.h
index 5196591..5a48eda 100644
--- a/src/gallium/include/pipe/p_defines.h
+++ b/src/gallium/include/pipe/p_defines.h
@@ -476,7 +476,8 @@ enum pipe_cap {
    PIPE_CAP_MIN_TEXEL_OFFSET = 50,
    PIPE_CAP_MAX_TEXEL_OFFSET = 51,
    PIPE_CAP_CONDITIONAL_RENDER = 52,
-   PIPE_CAP_TEXTURE_BARRIER = 53
+   PIPE_CAP_TEXTURE_BARRIER = 53,
+   PIPE_CAP_SHADER_OUTPUT_READ = 54
 };
 
 /* Shader caps not specific to any single stage */
-- 
1.7.7.1