[Mesa-dev] [PATCH 12/13] i965 vs: Separate IR visiting from code generation in vec4_visitor.

Paul Berry stereotype441 at gmail.com
Wed Nov 16 11:07:19 PST 2011


This patch separates vec4_visitor into a base class, vec4_generator,
and a derived class, vec4_visitor.  vec4_generator is responsible for
code generation, register allocation, and optimization; it is
independent of GLSL IR (with one trivial exception), and mostly
independent of the type of shader being compiled.  vec4_visitor is
responsible for visiting the GLSL IR and performing
vertex-shader-specific actions.

This helps pave the way for sharing code between VS and GS code
generation, by creating a new class for the parts of vec4_visitor that
are (or should soon be) independent of the type of shader being
compiled.  It is also important that the base class be as independent
of GLSL IR as possible, since our first use of the GS will be to
create a GS thread that performs transform feedback on Gen6, and this
thread will not be related to any GLSL IR.
---
 src/mesa/drivers/dri/i965/brw_vec4.cpp             |   10 +-
 src/mesa/drivers/dri/i965/brw_vec4.h               |  199 +++++++++++---------
 .../drivers/dri/i965/brw_vec4_copy_propagation.cpp |    2 +-
 src/mesa/drivers/dri/i965/brw_vec4_emit.cpp        |   80 ++++-----
 .../drivers/dri/i965/brw_vec4_reg_allocate.cpp     |    4 +-
 src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp     |  140 +++++++-------
 6 files changed, 228 insertions(+), 207 deletions(-)

diff --git a/src/mesa/drivers/dri/i965/brw_vec4.cpp b/src/mesa/drivers/dri/i965/brw_vec4.cpp
index 3971532..8632b9f 100644
--- a/src/mesa/drivers/dri/i965/brw_vec4.cpp
+++ b/src/mesa/drivers/dri/i965/brw_vec4.cpp
@@ -63,7 +63,7 @@ src_reg::equals(src_reg *r)
 }
 
 void
-vec4_visitor::calculate_live_intervals()
+vec4_generator::calculate_live_intervals()
 {
    int *def = ralloc_array(mem_ctx, int, virtual_grf_count);
    int *use = ralloc_array(mem_ctx, int, virtual_grf_count);
@@ -139,7 +139,7 @@ vec4_visitor::calculate_live_intervals()
 }
 
 bool
-vec4_visitor::virtual_grf_interferes(int a, int b)
+vec4_generator::virtual_grf_interferes(int a, int b)
 {
    int start = MAX2(this->virtual_grf_def[a], this->virtual_grf_def[b]);
    int end = MIN2(this->virtual_grf_use[a], this->virtual_grf_use[b]);
@@ -165,7 +165,7 @@ vec4_visitor::virtual_grf_interferes(int a, int b)
  * interfere with other regs.
  */
 bool
-vec4_visitor::dead_code_eliminate()
+vec4_generator::dead_code_eliminate()
 {
    bool progress = false;
    int pc = 0;
@@ -347,7 +347,7 @@ src_reg::is_one() const
  * instructions involving 0.
  */
 bool
-vec4_visitor::opt_algebraic()
+vec4_generator::opt_algebraic()
 {
    bool progress = false;
 
@@ -491,7 +491,7 @@ vec4_visitor::move_push_constants_to_pull_constants()
  * the GRF write directly to the MRF instead.
  */
 bool
-vec4_visitor::opt_compute_to_mrf()
+vec4_generator::opt_compute_to_mrf()
 {
    bool progress = false;
    int next_ip = 0;
diff --git a/src/mesa/drivers/dri/i965/brw_vec4.h b/src/mesa/drivers/dri/i965/brw_vec4.h
index 226413b..6eb6e5d 100644
--- a/src/mesa/drivers/dri/i965/brw_vec4.h
+++ b/src/mesa/drivers/dri/i965/brw_vec4.h
@@ -164,7 +164,7 @@ public:
    bool is_zero() const;
    bool is_one() const;
 
-   src_reg(class vec4_visitor *v, const struct glsl_type *type);
+   src_reg(class vec4_generator *v, const struct glsl_type *type);
 
    explicit src_reg(dst_reg reg);
 
@@ -218,7 +218,7 @@ public:
       this->fixed_hw_reg = reg;
    }
 
-   dst_reg(class vec4_visitor *v, const struct glsl_type *type);
+   dst_reg(class vec4_generator *v, const struct glsl_type *type);
 
    explicit dst_reg(src_reg reg);
 
@@ -241,7 +241,7 @@ public:
       return node;
    }
 
-   vec4_instruction(vec4_visitor *v, enum opcode opcode,
+   vec4_instruction(vec4_generator *v, enum opcode opcode,
 		    dst_reg dst = dst_reg(),
 		    src_reg src0 = src_reg(),
 		    src_reg src1 = src_reg(),
@@ -279,12 +279,11 @@ public:
    bool is_math();
 };
 
-class vec4_visitor : public ir_visitor
+class vec4_generator
 {
 public:
-   vec4_visitor(struct brw_vs_compile *c,
-		struct gl_shader_program *prog, struct brw_shader *shader);
-   ~vec4_visitor();
+   vec4_generator(struct brw_compile *p);
+   ~vec4_generator();
 
    dst_reg dst_null_f()
    {
@@ -297,14 +296,9 @@ public:
    }
 
    struct brw_context *brw;
-   const struct gl_vertex_program *vp;
    struct intel_context *intel;
    struct gl_context *ctx;
-   struct brw_vs_compile *c;
-   struct brw_vs_prog_data *prog_data;
    struct brw_compile *p;
-   struct brw_shader *shader;
-   struct gl_shader_program *prog;
    void *mem_ctx;
    exec_list instructions;
 
@@ -322,7 +316,6 @@ public:
    int virtual_grf_array_size;
    int *virtual_grf_def;
    int *virtual_grf_use;
-   dst_reg userplane[MAX_CLIP_PLANES];
 
    /**
     * This is the size to be used for an array with an element per
@@ -334,8 +327,6 @@ public:
 
    bool live_intervals_valid;
 
-   dst_reg *variable_storage(ir_variable *var);
-
    bool failed() const
    {
       return fail_msg != NULL;
@@ -348,63 +339,12 @@ public:
 
    src_reg src_reg_for_float(float val);
 
-   /**
-    * \name Visit methods
-    *
-    * As typical for the visitor pattern, there must be one \c visit method for
-    * each concrete subclass of \c ir_instruction.  Virtual base classes within
-    * the hierarchy should not have \c visit methods.
-    */
-   /*@{*/
-   virtual void visit(ir_variable *);
-   virtual void visit(ir_loop *);
-   virtual void visit(ir_loop_jump *);
-   virtual void visit(ir_function_signature *);
-   virtual void visit(ir_function *);
-   virtual void visit(ir_expression *);
-   virtual void visit(ir_swizzle *);
-   virtual void visit(ir_dereference_variable  *);
-   virtual void visit(ir_dereference_array *);
-   virtual void visit(ir_dereference_record *);
-   virtual void visit(ir_assignment *);
-   virtual void visit(ir_constant *);
-   virtual void visit(ir_call *);
-   virtual void visit(ir_return *);
-   virtual void visit(ir_discard *);
-   virtual void visit(ir_texture *);
-   virtual void visit(ir_if *);
-   /*@}*/
-
-   src_reg result;
-
-   /* Regs for vertex results.  Generated at ir_variable visiting time
-    * for the ir->location's used.
-    */
-   dst_reg output_reg[BRW_VERT_RESULT_MAX];
-   const char *output_reg_annotation[BRW_VERT_RESULT_MAX];
-   int uniform_size[MAX_UNIFORMS];
-   int uniform_vector_size[MAX_UNIFORMS];
-   int uniforms;
-
-   struct hash_table *variable_ht;
-
-   void run(void);
    void fail(const char *msg, ...);
 
    int virtual_grf_alloc(int size);
-   void setup_uniform_clipplane_values();
-   int setup_uniform_values(int loc, const glsl_type *type);
-   void setup_builtin_uniform_values(ir_variable *ir);
-   int setup_attributes(int payload_reg);
-   int setup_uniforms(int payload_reg);
-   int setup_payload();
    int reg_allocate_trivial(int first_non_payload_grf);
    int reg_allocate(int first_non_payload_grf);
    unsigned move_grf_array_access_to_scratch();
-   void move_uniform_array_access_to_pull_constants();
-   void move_push_constants_to_pull_constants();
-   void split_uniform_registers();
-   void pack_uniform_registers();
    void calculate_live_intervals();
    bool dead_code_eliminate();
    bool virtual_grf_interferes(int a, int b);
@@ -457,17 +397,6 @@ public:
 			       vec4_instruction *pre_rhs_inst,
 			       vec4_instruction *last_rhs_inst);
 
-   /** Walks an exec_list of ir_instruction and sends it through this visitor. */
-   void visit_instructions(const exec_list *list);
-
-   void emit_bool_to_cond_code(ir_rvalue *ir, uint32_t *predicate);
-   void emit_if_gen6(ir_if *ir);
-
-   void emit_block_move(dst_reg *dst, src_reg *src,
-			const struct glsl_type *type, uint32_t predicate);
-
-   void emit_constant_values(dst_reg *dst, ir_constant *value);
-
    /**
     * Emit the correct dot-product instruction for the type of arguments
     */
@@ -489,13 +418,6 @@ public:
    void emit_math2_gen4(enum opcode opcode, dst_reg dst, src_reg src0, src_reg src1);
    void emit_math(enum opcode opcode, dst_reg dst, src_reg src0, src_reg src1);
 
-   void emit_ndc_computation();
-   void emit_psiz_and_flags(struct brw_reg reg);
-   void emit_clip_distances(struct brw_reg reg, int offset);
-   void emit_generic_urb_slot(dst_reg reg, int vert_result);
-   void emit_urb_slot(int mrf, int vert_result);
-   void emit_urb_writes(void);
-
    src_reg get_scratch_offset(vec4_instruction *inst,
 			      src_reg *reladdr, int reg_offset);
    src_reg get_pull_constant_offset(vec4_instruction *inst,
@@ -513,11 +435,19 @@ public:
 				src_reg orig_src,
 				int base_offset);
 
-   bool try_emit_sat(ir_expression *ir);
    void resolve_ud_negate(src_reg *reg);
 
-   bool get_debug_flag() const;
-   const char *get_debug_name() const;
+   /**
+    * Return a bool indicating whether debugging output should be generated
+    * for this shader.
+    */
+   virtual bool get_debug_flag() const = 0;
+
+   /**
+    * Return a string describing the program being compiled, for debugging
+    * purposes.  Caller should not free this string.
+    */
+   virtual const char *get_debug_name() const = 0;
 
    int generate_code(int first_non_payload_grf);
    void generate_vs_instruction(vec4_instruction *inst,
@@ -559,6 +489,101 @@ public:
    dst_reg get_assignment_lhs(ir_dereference *ir);
 };
 
+class vec4_visitor : public vec4_generator, public ir_visitor
+{
+public:
+   vec4_visitor(struct brw_vs_compile *c,
+		struct gl_shader_program *prog, struct brw_shader *shader);
+
+   ~vec4_visitor();
+
+   const struct gl_vertex_program *vp;
+   struct brw_vs_compile *c;
+   struct brw_vs_prog_data *prog_data;
+   struct brw_shader *shader;
+   struct gl_shader_program *prog;
+
+   dst_reg userplane[MAX_CLIP_PLANES];
+
+   dst_reg *variable_storage(ir_variable *var);
+
+   /**
+    * \name Visit methods
+    *
+    * As typical for the visitor pattern, there must be one \c visit method for
+    * each concrete subclass of \c ir_instruction.  Virtual base classes within
+    * the hierarchy should not have \c visit methods.
+    */
+   /*@{*/
+   virtual void visit(ir_variable *);
+   virtual void visit(ir_loop *);
+   virtual void visit(ir_loop_jump *);
+   virtual void visit(ir_function_signature *);
+   virtual void visit(ir_function *);
+   virtual void visit(ir_expression *);
+   virtual void visit(ir_swizzle *);
+   virtual void visit(ir_dereference_variable  *);
+   virtual void visit(ir_dereference_array *);
+   virtual void visit(ir_dereference_record *);
+   virtual void visit(ir_assignment *);
+   virtual void visit(ir_constant *);
+   virtual void visit(ir_call *);
+   virtual void visit(ir_return *);
+   virtual void visit(ir_discard *);
+   virtual void visit(ir_texture *);
+   virtual void visit(ir_if *);
+   /*@}*/
+
+   src_reg result;
+
+   /* Regs for vertex results.  Generated at ir_variable visiting time
+    * for the ir->location's used.
+    */
+   dst_reg output_reg[BRW_VERT_RESULT_MAX];
+   const char *output_reg_annotation[BRW_VERT_RESULT_MAX];
+   int uniform_size[MAX_UNIFORMS];
+   int uniform_vector_size[MAX_UNIFORMS];
+   int uniforms;
+
+   struct hash_table *variable_ht;
+
+   void run(void);
+
+   void setup_uniform_clipplane_values();
+   int setup_uniform_values(int loc, const glsl_type *type);
+   void setup_builtin_uniform_values(ir_variable *ir);
+   int setup_attributes(int payload_reg);
+   int setup_uniforms(int payload_reg);
+   int setup_payload();
+   void move_uniform_array_access_to_pull_constants();
+   void move_push_constants_to_pull_constants();
+   void split_uniform_registers();
+   void pack_uniform_registers();
+
+   /** Walks an exec_list of ir_instruction and sends it through this visitor. */
+   void visit_instructions(const exec_list *list);
+
+   void emit_bool_to_cond_code(ir_rvalue *ir, uint32_t *predicate);
+   void emit_if_gen6(ir_if *ir);
+
+   void emit_block_move(dst_reg *dst, src_reg *src,
+			const struct glsl_type *type, uint32_t predicate);
+
+   void emit_constant_values(dst_reg *dst, ir_constant *value);
+
+   void emit_ndc_computation();
+   void emit_psiz_and_flags(struct brw_reg reg);
+   void emit_clip_distances(struct brw_reg reg, int offset);
+   void emit_generic_urb_slot(dst_reg reg, int vert_result);
+   void emit_urb_slot(int mrf, int vert_result);
+   void emit_urb_writes(void);
+
+   bool try_emit_sat(ir_expression *ir);
+
+   virtual bool get_debug_flag() const;
+   virtual const char *get_debug_name() const;
+};
+
 } /* namespace brw */
 
 #endif /* BRW_VEC4_H */
diff --git a/src/mesa/drivers/dri/i965/brw_vec4_copy_propagation.cpp b/src/mesa/drivers/dri/i965/brw_vec4_copy_propagation.cpp
index 93ae3d6..48d3ba4 100644
--- a/src/mesa/drivers/dri/i965/brw_vec4_copy_propagation.cpp
+++ b/src/mesa/drivers/dri/i965/brw_vec4_copy_propagation.cpp
@@ -229,7 +229,7 @@ try_copy_propagation(struct intel_context *intel,
 }
 
 bool
-vec4_visitor::opt_copy_propagation()
+vec4_generator::opt_copy_propagation()
 {
    bool progress = false;
    src_reg *cur_value[virtual_grf_reg_count][4];
diff --git a/src/mesa/drivers/dri/i965/brw_vec4_emit.cpp b/src/mesa/drivers/dri/i965/brw_vec4_emit.cpp
index 5724a29..8461d14 100644
--- a/src/mesa/drivers/dri/i965/brw_vec4_emit.cpp
+++ b/src/mesa/drivers/dri/i965/brw_vec4_emit.cpp
@@ -247,9 +247,9 @@ vec4_instruction::get_src(int i)
 }
 
 void
-vec4_visitor::generate_math1_gen4(vec4_instruction *inst,
-				  struct brw_reg dst,
-				  struct brw_reg src)
+vec4_generator::generate_math1_gen4(vec4_instruction *inst,
+                                    struct brw_reg dst,
+                                    struct brw_reg src)
 {
    brw_math(p,
 	    dst,
@@ -271,9 +271,9 @@ check_gen6_math_src_arg(struct brw_reg src)
 }
 
 void
-vec4_visitor::generate_math1_gen6(vec4_instruction *inst,
-				  struct brw_reg dst,
-				  struct brw_reg src)
+vec4_generator::generate_math1_gen6(vec4_instruction *inst,
+                                    struct brw_reg dst,
+                                    struct brw_reg src)
 {
    /* Can't do writemask because math can't be align16. */
    assert(dst.dw1.bits.writemask == WRITEMASK_XYZW);
@@ -292,10 +292,10 @@ vec4_visitor::generate_math1_gen6(vec4_instruction *inst,
 }
 
 void
-vec4_visitor::generate_math2_gen7(vec4_instruction *inst,
-				  struct brw_reg dst,
-				  struct brw_reg src0,
-				  struct brw_reg src1)
+vec4_generator::generate_math2_gen7(vec4_instruction *inst,
+                                    struct brw_reg dst,
+                                    struct brw_reg src0,
+                                    struct brw_reg src1)
 {
    brw_math2(p,
 	     dst,
@@ -304,10 +304,10 @@ vec4_visitor::generate_math2_gen7(vec4_instruction *inst,
 }
 
 void
-vec4_visitor::generate_math2_gen6(vec4_instruction *inst,
-				  struct brw_reg dst,
-				  struct brw_reg src0,
-				  struct brw_reg src1)
+vec4_generator::generate_math2_gen6(vec4_instruction *inst,
+                                    struct brw_reg dst,
+                                    struct brw_reg src0,
+                                    struct brw_reg src1)
 {
    /* Can't do writemask because math can't be align16. */
    assert(dst.dw1.bits.writemask == WRITEMASK_XYZW);
@@ -324,10 +324,10 @@ vec4_visitor::generate_math2_gen6(vec4_instruction *inst,
 }
 
 void
-vec4_visitor::generate_math2_gen4(vec4_instruction *inst,
-				  struct brw_reg dst,
-				  struct brw_reg src0,
-				  struct brw_reg src1)
+vec4_generator::generate_math2_gen4(vec4_instruction *inst,
+                                    struct brw_reg dst,
+                                    struct brw_reg src0,
+                                    struct brw_reg src1)
 {
    /* From the Ironlake PRM, Volume 4, Part 1, Section 6.1.13
     * "Message Payload":
@@ -355,7 +355,7 @@ vec4_visitor::generate_math2_gen4(vec4_instruction *inst,
 }
 
 void
-vec4_visitor::generate_urb_write(vec4_instruction *inst)
+vec4_generator::generate_urb_write(vec4_instruction *inst)
 {
    brw_urb_WRITE(p,
 		 brw_null_reg(), /* dest */
@@ -372,8 +372,8 @@ vec4_visitor::generate_urb_write(vec4_instruction *inst)
 }
 
 void
-vec4_visitor::generate_oword_dual_block_offsets(struct brw_reg m1,
-						struct brw_reg index)
+vec4_generator::generate_oword_dual_block_offsets(struct brw_reg m1,
+                                                  struct brw_reg index)
 {
    int second_vertex_offset;
 
@@ -410,9 +410,9 @@ vec4_visitor::generate_oword_dual_block_offsets(struct brw_reg m1,
 }
 
 void
-vec4_visitor::generate_scratch_read(vec4_instruction *inst,
-				    struct brw_reg dst,
-				    struct brw_reg index)
+vec4_generator::generate_scratch_read(vec4_instruction *inst,
+                                      struct brw_reg dst,
+                                      struct brw_reg index)
 {
    struct brw_reg header = brw_vec8_grf(0, 0);
 
@@ -448,10 +448,10 @@ vec4_visitor::generate_scratch_read(vec4_instruction *inst,
 }
 
 void
-vec4_visitor::generate_scratch_write(vec4_instruction *inst,
-				     struct brw_reg dst,
-				     struct brw_reg src,
-				     struct brw_reg index)
+vec4_generator::generate_scratch_write(vec4_instruction *inst,
+                                       struct brw_reg dst,
+                                       struct brw_reg src,
+                                       struct brw_reg index)
 {
    struct brw_reg header = brw_vec8_grf(0, 0);
    bool write_commit;
@@ -521,9 +521,9 @@ vec4_visitor::generate_scratch_write(vec4_instruction *inst,
 }
 
 void
-vec4_visitor::generate_pull_constant_load(vec4_instruction *inst,
-					  struct brw_reg dst,
-					  struct brw_reg index)
+vec4_generator::generate_pull_constant_load(vec4_instruction *inst,
+                                            struct brw_reg dst,
+                                            struct brw_reg index)
 {
    struct brw_reg header = brw_vec8_grf(0, 0);
 
@@ -559,9 +559,9 @@ vec4_visitor::generate_pull_constant_load(vec4_instruction *inst,
 }
 
 void
-vec4_visitor::generate_vs_instruction(vec4_instruction *instruction,
-				      struct brw_reg dst,
-				      struct brw_reg *src)
+vec4_generator::generate_vs_instruction(vec4_instruction *instruction,
+                                        struct brw_reg dst,
+                                        struct brw_reg *src)
 {
    vec4_instruction *inst = (vec4_instruction *)instruction;
 
@@ -622,7 +622,7 @@ vec4_visitor::generate_vs_instruction(vec4_instruction *instruction,
 }
 
 void
-vec4_visitor::optimize()
+vec4_generator::optimize()
 {
    bool progress;
    do {
@@ -667,20 +667,12 @@ vec4_visitor::run()
    prog_data->total_grf = generate_code(first_non_payload_grf);
 }
 
-/**
- * Return a bool indicating whether debugging output should be generated
- * for this shader.
- */
 bool
 vec4_visitor::get_debug_flag() const
 {
    return INTEL_DEBUG & DEBUG_VS;
 }
 
-/**
- * Return a string describing the program being compiled, for debugging
- * purposes.  Caller should not free this string.
- */
 const char *
 vec4_visitor::get_debug_name() const
 {
@@ -688,7 +680,7 @@ vec4_visitor::get_debug_name() const
 }
 
 int
-vec4_visitor::generate_code(int first_non_payload_grf)
+vec4_generator::generate_code(int first_non_payload_grf)
 {
    bool debug_flag = get_debug_flag();
    int last_native_inst = 0;
diff --git a/src/mesa/drivers/dri/i965/brw_vec4_reg_allocate.cpp b/src/mesa/drivers/dri/i965/brw_vec4_reg_allocate.cpp
index f6db9b4..523b0d9 100644
--- a/src/mesa/drivers/dri/i965/brw_vec4_reg_allocate.cpp
+++ b/src/mesa/drivers/dri/i965/brw_vec4_reg_allocate.cpp
@@ -42,7 +42,7 @@ assign(int *reg_hw_locations, reg *reg)
 }
 
 int
-vec4_visitor::reg_allocate_trivial(int first_non_payload_grf)
+vec4_generator::reg_allocate_trivial(int first_non_payload_grf)
 {
    int hw_reg_mapping[this->virtual_grf_count];
    bool virtual_grf_used[this->virtual_grf_count];
@@ -142,7 +142,7 @@ brw_alloc_reg_set_for_classes(struct brw_context *brw,
 }
 
 int
-vec4_visitor::reg_allocate(int first_non_payload_grf)
+vec4_generator::reg_allocate(int first_non_payload_grf)
 {
    int hw_reg_mapping[virtual_grf_count];
    int first_assigned_grf = first_non_payload_grf;
diff --git a/src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp b/src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp
index cf71ef4..f1d4f65 100644
--- a/src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp
+++ b/src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp
@@ -72,7 +72,7 @@ dst_reg::dst_reg(src_reg reg)
    this->fixed_hw_reg = reg.fixed_hw_reg;
 }
 
-vec4_instruction::vec4_instruction(vec4_visitor *v,
+vec4_instruction::vec4_instruction(vec4_generator *v,
 				   enum opcode opcode, dst_reg dst,
 				   src_reg src0, src_reg src1, src_reg src2)
 {
@@ -86,7 +86,7 @@ vec4_instruction::vec4_instruction(vec4_visitor *v,
 }
 
 vec4_instruction *
-vec4_visitor::emit(vec4_instruction *inst)
+vec4_generator::emit(vec4_instruction *inst)
 {
    this->instructions.push_tail(inst);
 
@@ -94,7 +94,7 @@ vec4_visitor::emit(vec4_instruction *inst)
 }
 
 vec4_instruction *
-vec4_visitor::emit_before(vec4_instruction *inst, vec4_instruction *new_inst)
+vec4_generator::emit_before(vec4_instruction *inst, vec4_instruction *new_inst)
 {
    new_inst->ir = inst->ir;
    new_inst->annotation = inst->annotation;
@@ -105,8 +105,8 @@ vec4_visitor::emit_before(vec4_instruction *inst, vec4_instruction *new_inst)
 }
 
 vec4_instruction *
-vec4_visitor::emit(enum opcode opcode, dst_reg dst,
-		   src_reg src0, src_reg src1, src_reg src2)
+vec4_generator::emit(enum opcode opcode, dst_reg dst,
+                     src_reg src0, src_reg src1, src_reg src2)
 {
    return emit(new(mem_ctx) vec4_instruction(this, opcode, dst,
 					     src0, src1, src2));
@@ -114,26 +114,26 @@ vec4_visitor::emit(enum opcode opcode, dst_reg dst,
 
 
 vec4_instruction *
-vec4_visitor::emit(enum opcode opcode, dst_reg dst, src_reg src0, src_reg src1)
+vec4_generator::emit(enum opcode opcode, dst_reg dst, src_reg src0, src_reg src1)
 {
    return emit(new(mem_ctx) vec4_instruction(this, opcode, dst, src0, src1));
 }
 
 vec4_instruction *
-vec4_visitor::emit(enum opcode opcode, dst_reg dst, src_reg src0)
+vec4_generator::emit(enum opcode opcode, dst_reg dst, src_reg src0)
 {
    return emit(new(mem_ctx) vec4_instruction(this, opcode, dst, src0));
 }
 
 vec4_instruction *
-vec4_visitor::emit(enum opcode opcode)
+vec4_generator::emit(enum opcode opcode)
 {
    return emit(new(mem_ctx) vec4_instruction(this, opcode, dst_reg()));
 }
 
 #define ALU1(op)							\
    vec4_instruction *							\
-   vec4_visitor::op(dst_reg dst, src_reg src0)				\
+   vec4_generator::op(dst_reg dst, src_reg src0)			\
    {									\
       return new(mem_ctx) vec4_instruction(this, BRW_OPCODE_##op, dst,	\
 					   src0);			\
@@ -141,7 +141,7 @@ vec4_visitor::emit(enum opcode opcode)
 
 #define ALU2(op)							\
    vec4_instruction *							\
-   vec4_visitor::op(dst_reg dst, src_reg src0, src_reg src1)		\
+   vec4_generator::op(dst_reg dst, src_reg src0, src_reg src1)		\
    {									\
       return new(mem_ctx) vec4_instruction(this, BRW_OPCODE_##op, dst,	\
 					   src0, src1);			\
@@ -164,7 +164,7 @@ ALU2(DP4)
 
 /** Gen4 predicated IF. */
 vec4_instruction *
-vec4_visitor::IF(uint32_t predicate)
+vec4_generator::IF(uint32_t predicate)
 {
    vec4_instruction *inst;
 
@@ -176,7 +176,7 @@ vec4_visitor::IF(uint32_t predicate)
 
 /** Gen6+ IF with embedded comparison. */
 vec4_instruction *
-vec4_visitor::IF(src_reg src0, src_reg src1, uint32_t condition)
+vec4_generator::IF(src_reg src0, src_reg src1, uint32_t condition)
 {
    assert(intel->gen >= 6);
 
@@ -198,7 +198,7 @@ vec4_visitor::IF(src_reg src0, src_reg src1, uint32_t condition)
  * the flag register with the packed 16 bits of the result.
  */
 vec4_instruction *
-vec4_visitor::CMP(dst_reg dst, src_reg src0, src_reg src1, uint32_t condition)
+vec4_generator::CMP(dst_reg dst, src_reg src0, src_reg src1, uint32_t condition)
 {
    vec4_instruction *inst;
 
@@ -222,7 +222,7 @@ vec4_visitor::CMP(dst_reg dst, src_reg src0, src_reg src1, uint32_t condition)
 }
 
 vec4_instruction *
-vec4_visitor::SCRATCH_READ(dst_reg dst, src_reg index)
+vec4_generator::SCRATCH_READ(dst_reg dst, src_reg index)
 {
    vec4_instruction *inst;
 
@@ -235,7 +235,7 @@ vec4_visitor::SCRATCH_READ(dst_reg dst, src_reg index)
 }
 
 vec4_instruction *
-vec4_visitor::SCRATCH_WRITE(dst_reg dst, src_reg src, src_reg index)
+vec4_generator::SCRATCH_WRITE(dst_reg dst, src_reg src, src_reg index)
 {
    vec4_instruction *inst;
 
@@ -248,7 +248,7 @@ vec4_visitor::SCRATCH_WRITE(dst_reg dst, src_reg src, src_reg index)
 }
 
 void
-vec4_visitor::emit_dp(dst_reg dst, src_reg src0, src_reg src1, unsigned elements)
+vec4_generator::emit_dp(dst_reg dst, src_reg src0, src_reg src1, unsigned elements)
 {
    static enum opcode dot_opcodes[] = {
       BRW_OPCODE_DP2, BRW_OPCODE_DP3, BRW_OPCODE_DP4
@@ -258,7 +258,7 @@ vec4_visitor::emit_dp(dst_reg dst, src_reg src0, src_reg src1, unsigned elements
 }
 
 void
-vec4_visitor::emit_math1_gen6(enum opcode opcode, dst_reg dst, src_reg src)
+vec4_generator::emit_math1_gen6(enum opcode opcode, dst_reg dst, src_reg src)
 {
    /* The gen6 math instruction ignores the source modifiers --
     * swizzle, abs, negate, and at least some parts of the register
@@ -288,7 +288,7 @@ vec4_visitor::emit_math1_gen6(enum opcode opcode, dst_reg dst, src_reg src)
 }
 
 void
-vec4_visitor::emit_math1_gen4(enum opcode opcode, dst_reg dst, src_reg src)
+vec4_generator::emit_math1_gen4(enum opcode opcode, dst_reg dst, src_reg src)
 {
    vec4_instruction *inst = emit(opcode, dst, src);
    inst->base_mrf = 1;
@@ -296,7 +296,7 @@ vec4_visitor::emit_math1_gen4(enum opcode opcode, dst_reg dst, src_reg src)
 }
 
 void
-vec4_visitor::emit_math(opcode opcode, dst_reg dst, src_reg src)
+vec4_generator::emit_math(opcode opcode, dst_reg dst, src_reg src)
 {
    switch (opcode) {
    case SHADER_OPCODE_RCP:
@@ -320,8 +320,8 @@ vec4_visitor::emit_math(opcode opcode, dst_reg dst, src_reg src)
 }
 
 void
-vec4_visitor::emit_math2_gen6(enum opcode opcode,
-			      dst_reg dst, src_reg src0, src_reg src1)
+vec4_generator::emit_math2_gen6(enum opcode opcode,
+                                dst_reg dst, src_reg src0, src_reg src1)
 {
    src_reg expanded;
 
@@ -357,8 +357,8 @@ vec4_visitor::emit_math2_gen6(enum opcode opcode,
 }
 
 void
-vec4_visitor::emit_math2_gen4(enum opcode opcode,
-			      dst_reg dst, src_reg src0, src_reg src1)
+vec4_generator::emit_math2_gen4(enum opcode opcode,
+                                dst_reg dst, src_reg src0, src_reg src1)
 {
    vec4_instruction *inst = emit(opcode, dst, src0, src1);
    inst->base_mrf = 1;
@@ -366,8 +366,8 @@ vec4_visitor::emit_math2_gen4(enum opcode opcode,
 }
 
 void
-vec4_visitor::emit_math(enum opcode opcode,
-			dst_reg dst, src_reg src0, src_reg src1)
+vec4_generator::emit_math(enum opcode opcode,
+                          dst_reg dst, src_reg src0, src_reg src1)
 {
    switch (opcode) {
    case SHADER_OPCODE_POW:
@@ -440,7 +440,7 @@ type_size(const struct glsl_type *type)
 }
 
 int
-vec4_visitor::virtual_grf_alloc(int size)
+vec4_generator::virtual_grf_alloc(int size)
 {
    if (virtual_grf_array_size <= virtual_grf_count) {
       if (virtual_grf_array_size == 0)
@@ -458,7 +458,7 @@ vec4_visitor::virtual_grf_alloc(int size)
    return virtual_grf_count++;
 }
 
-src_reg::src_reg(class vec4_visitor *v, const struct glsl_type *type)
+src_reg::src_reg(class vec4_generator *v, const struct glsl_type *type)
 {
    init();
 
@@ -474,7 +474,7 @@ src_reg::src_reg(class vec4_visitor *v, const struct glsl_type *type)
    this->type = brw_type_for_base_type(type);
 }
 
-dst_reg::dst_reg(class vec4_visitor *v, const struct glsl_type *type)
+dst_reg::dst_reg(class vec4_generator *v, const struct glsl_type *type)
 {
    init();
 
@@ -1482,7 +1482,7 @@ vec4_visitor::get_assignment_lhs(ir_dereference *ir)
 
 void
 vec4_visitor::emit_block_move(dst_reg *dst, src_reg *src,
-			      const struct glsl_type *type, uint32_t predicate)
+                              const struct glsl_type *type, uint32_t predicate)
 {
    if (type->base_type == GLSL_TYPE_STRUCT) {
       for (unsigned int i = 0; i < type->length; i++) {
@@ -1537,11 +1537,11 @@ vec4_visitor::emit_block_move(dst_reg *dst, src_reg *src,
  * later without real UD chain information.
  */
 bool
-vec4_visitor::try_rewrite_rhs_to_dst(ir_assignment *ir,
-				     dst_reg dst,
-				     src_reg src,
-				     vec4_instruction *pre_rhs_inst,
-				     vec4_instruction *last_rhs_inst)
+vec4_generator::try_rewrite_rhs_to_dst(ir_assignment *ir,
+                                       dst_reg dst,
+                                       src_reg src,
+                                       vec4_instruction *pre_rhs_inst,
+                                       vec4_instruction *last_rhs_inst)
 {
    /* This could be supported, but it would take more smarts. */
    if (ir->condition)
@@ -2089,8 +2089,8 @@ vec4_visitor::emit_urb_writes()
 }
 
 src_reg
-vec4_visitor::get_scratch_offset(vec4_instruction *inst,
-				 src_reg *reladdr, int reg_offset)
+vec4_generator::get_scratch_offset(vec4_instruction *inst,
+                                   src_reg *reladdr, int reg_offset)
 {
    /* Because we store the values to scratch interleaved like our
     * vertex data, we need to scale the vec4 index by 2.
@@ -2117,8 +2117,8 @@ vec4_visitor::get_scratch_offset(vec4_instruction *inst,
 }
 
 src_reg
-vec4_visitor::get_pull_constant_offset(vec4_instruction *inst,
-				       src_reg *reladdr, int reg_offset)
+vec4_generator::get_pull_constant_offset(vec4_instruction *inst,
+                                         src_reg *reladdr, int reg_offset)
 {
    if (reladdr) {
       src_reg index = src_reg(this, glsl_type::int_type);
@@ -2144,9 +2144,9 @@ vec4_visitor::get_pull_constant_offset(vec4_instruction *inst,
  * from scratch space at @base_offset to @temp.
  */
 void
-vec4_visitor::emit_scratch_read(vec4_instruction *inst,
-				dst_reg temp, src_reg orig_src,
-				int base_offset)
+vec4_generator::emit_scratch_read(vec4_instruction *inst,
+                                  dst_reg temp, src_reg orig_src,
+                                  int base_offset)
 {
    int reg_offset = base_offset + orig_src.reg_offset;
    src_reg index = get_scratch_offset(inst, orig_src.reladdr, reg_offset);
@@ -2159,9 +2159,9 @@ vec4_visitor::emit_scratch_read(vec4_instruction *inst,
  * to @orig_dst to scratch space at @base_offset, from @temp.
  */
 void
-vec4_visitor::emit_scratch_write(vec4_instruction *inst,
-				 src_reg temp, dst_reg orig_dst,
-				 int base_offset)
+vec4_generator::emit_scratch_write(vec4_instruction *inst,
+                                   src_reg temp, dst_reg orig_dst,
+                                   int base_offset)
 {
    int reg_offset = base_offset + orig_dst.reg_offset;
    src_reg index = get_scratch_offset(inst, orig_dst.reladdr, reg_offset);
@@ -2182,7 +2182,7 @@ vec4_visitor::emit_scratch_write(vec4_instruction *inst,
  * access to scratch space.
  */
 unsigned
-vec4_visitor::move_grf_array_access_to_scratch()
+vec4_generator::move_grf_array_access_to_scratch()
 {
    int scratch_loc[this->virtual_grf_count];
    unsigned last_scratch = 0;
@@ -2262,9 +2262,9 @@ vec4_visitor::move_grf_array_access_to_scratch()
  * from the pull constant buffer (surface) at @base_offset to @temp.
  */
 void
-vec4_visitor::emit_pull_constant_load(vec4_instruction *inst,
-				      dst_reg temp, src_reg orig_src,
-				      int base_offset)
+vec4_generator::emit_pull_constant_load(vec4_instruction *inst,
+                                        dst_reg temp, src_reg orig_src,
+                                        int base_offset)
 {
    int reg_offset = base_offset + orig_src.reg_offset;
    src_reg index = get_pull_constant_offset(inst, orig_src.reladdr, reg_offset);
@@ -2351,7 +2351,7 @@ vec4_visitor::move_uniform_array_access_to_pull_constants()
 }
 
 void
-vec4_visitor::resolve_ud_negate(src_reg *reg)
+vec4_generator::resolve_ud_negate(src_reg *reg)
 {
    if (reg->type != BRW_REGISTER_TYPE_UD ||
        !reg->negate)
@@ -2362,17 +2362,12 @@ vec4_visitor::resolve_ud_negate(src_reg *reg)
    *reg = temp;
 }
 
-vec4_visitor::vec4_visitor(struct brw_vs_compile *c,
-			   struct gl_shader_program *prog,
-			   struct brw_shader *shader)
+vec4_generator::vec4_generator(struct brw_compile *p)
 {
-   this->c = c;
-   this->p = &c->func;
+   this->p = p;
    this->brw = p->brw;
    this->intel = &brw->intel;
    this->ctx = &intel->ctx;
-   this->prog = prog;
-   this->shader = shader;
 
    this->mem_ctx = ralloc_context(NULL);
    this->fail_msg = NULL;
@@ -2380,15 +2375,6 @@ vec4_visitor::vec4_visitor(struct brw_vs_compile *c,
    this->base_ir = NULL;
    this->current_annotation = NULL;
 
-   this->c = c;
-   this->vp = (struct gl_vertex_program *)
-     prog->_LinkedShaders[MESA_SHADER_VERTEX]->Program;
-   this->prog_data = &c->prog_data;
-
-   this->variable_ht = hash_table_ctor(0,
-				       hash_table_pointer_hash,
-				       hash_table_pointer_compare);
-
    this->virtual_grf_def = NULL;
    this->virtual_grf_use = NULL;
    this->virtual_grf_sizes = NULL;
@@ -2397,23 +2383,41 @@ vec4_visitor::vec4_visitor(struct brw_vs_compile *c,
    this->virtual_grf_reg_count = 0;
    this->virtual_grf_array_size = 0;
    this->live_intervals_valid = false;
+}
 
-   this->uniforms = 0;
+vec4_visitor::vec4_visitor(struct brw_vs_compile *c,
+                           struct gl_shader_program *prog,
+                           struct brw_shader *shader)
+   : vec4_generator(&c->func)
+{
+   this->c = c;
+   this->prog = prog;
+   this->shader = shader;
+
+   this->vp = (struct gl_vertex_program *)
+     prog->_LinkedShaders[MESA_SHADER_VERTEX]->Program;
+   this->prog_data = &c->prog_data;
 
    this->variable_ht = hash_table_ctor(0,
 				       hash_table_pointer_hash,
 				       hash_table_pointer_compare);
+
+   this->uniforms = 0;
 }
 
-vec4_visitor::~vec4_visitor()
+vec4_generator::~vec4_generator()
 {
    ralloc_free(this->mem_ctx);
+}
+
+vec4_visitor::~vec4_visitor()
+{
    hash_table_dtor(this->variable_ht);
 }
 
 
 void
-vec4_visitor::fail(const char *format, ...)
+vec4_generator::fail(const char *format, ...)
 {
    va_list va;
    char *msg;
-- 
1.7.6.4



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