[Mesa-dev] [PATCH 26/41] i965/gen6: Manipulate state batches for HiZ meta-ops

[Eric Anholt]

On Thu, 17 Nov 2011 19:58:53 -0800, Chad Versace <chad.versace at linux.intel.com> wrote:
> A lot of the state manipulation is handled by the meta-op state setup.
> However, some batches need manual intervention.
> 
> Signed-off-by: Chad Versace <chad.versace at linux.intel.com>
> ---
>  src/mesa/drivers/dri/i965/brw_draw.c          |    9 ++++++++-
>  src/mesa/drivers/dri/i965/gen6_clip_state.c   |   17 +++++++++++++++++
>  src/mesa/drivers/dri/i965/gen6_depthstencil.c |   22 ++++++++++++++++++++--
>  src/mesa/drivers/dri/i965/gen6_sf_state.c     |   15 +++++++++++++--
>  src/mesa/drivers/dri/i965/gen6_wm_state.c     |   17 +++++++++++++++++
>  5 files changed, 75 insertions(+), 5 deletions(-)
> 
> diff --git a/src/mesa/drivers/dri/i965/brw_draw.c b/src/mesa/drivers/dri/i965/brw_draw.c
> index 1571fb7..d2ae087 100644
> --- a/src/mesa/drivers/dri/i965/brw_draw.c
> +++ b/src/mesa/drivers/dri/i965/brw_draw.c
> @@ -117,10 +117,17 @@ static void brw_set_prim(struct brw_context *brw,
>  static void gen6_set_prim(struct brw_context *brw,
>                            const struct _mesa_prim *prim)
>  {
> -   uint32_t hw_prim = prim_to_hw_prim[prim->mode];
> +   uint32_t hw_prim;
>  
>     DBG("PRIM: %s\n", _mesa_lookup_enum_by_nr(prim->mode));
>  
> +   if (brw->hiz.op) {
> +      assert(prim->mode == GL_TRIANGLES);
> +      hw_prim = _3DPRIM_RECTLIST;
> +   } else {
> +      hw_prim = prim_to_hw_prim[prim->mode];
> +   }
> +
>     if (hw_prim != brw->primitive) {
>        brw->primitive = hw_prim;
>        brw->state.dirty.brw |= BRW_NEW_PRIMITIVE;

> diff --git a/src/mesa/drivers/dri/i965/gen6_depthstencil.c b/src/mesa/drivers/dri/i965/gen6_depthstencil.c
> index 72e8687..4eb2012 100644
> --- a/src/mesa/drivers/dri/i965/gen6_depthstencil.c
> +++ b/src/mesa/drivers/dri/i965/gen6_depthstencil.c
> @@ -77,10 +77,28 @@ gen6_upload_depth_stencil_state(struct brw_context *brw)
>     }
>  
>     /* _NEW_DEPTH */
> -   if (ctx->Depth.Test) {
> -      ds->ds2.depth_test_enable = 1;
> +   if (ctx->Depth.Test || brw->hiz.op) {
>        ds->ds2.depth_test_func = intel_translate_compare_func(ctx->Depth.Func);
>        ds->ds2.depth_write_enable = ctx->Depth.Mask;
> +
> +      /* See the following sections of the Sandy Bridge PRM, Volume 1, Part2:
> +       *   - 7.5.3.1 Depth Buffer Clear
> +       *   - 7.5.3.2 Depth Buffer Resolve
> +       *   - 7.5.3.3 Hierarchical Depth Buffer Resolve
> +       */
> +      switch (brw->hiz.op) {
> +      case BRW_HIZ_OP_NONE:
> +      case BRW_HIZ_OP_DEPTH_RESOLVE:
> +         ds->ds2.depth_test_enable = 1;
> +         break;
> +      case BRW_HIZ_OP_DEPTH_CLEAR:
> +      case BRW_HIZ_OP_HIZ_RESOLVE:
> +         ds->ds2.depth_test_enable = 0;
> +         break;
> +      default:
> +         assert(0);
> +         break;
> +      }

The meta-op should just always set depth test appropriately instead of
adding this hunk, I think.  It already does in one case.
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