[Mesa-dev] [PATCH] i965/gen6: Fix GPU hang when using stencil buffer without depth

[Chad Versace]

Set the "Tiled Surface" bit in 3DSTATE_DEPTH_BUFFER. From the BSpec:
   [DevGT+]: This field must be set to TRUE.

Fixes GPU hangs on following the Piglit tests:
   hiz-stencil-test-fbo-d0-s8
   hiz-stencil-read-fbo-d0-s8

Signed-off-by: Chad Versace <chad.versace at linux.intel.com>
---
 src/mesa/drivers/dri/i965/brw_misc_state.c |    4 ++++
 1 files changed, 4 insertions(+), 0 deletions(-)

diff --git a/src/mesa/drivers/dri/i965/brw_misc_state.c b/src/mesa/drivers/dri/i965/brw_misc_state.c
index 17da460..d5c66a4 100644
--- a/src/mesa/drivers/dri/i965/brw_misc_state.c
+++ b/src/mesa/drivers/dri/i965/brw_misc_state.c
@@ -278,6 +278,9 @@ static void emit_depthbuffer(struct brw_context *brw)
        *
        *     [DevGT]: This field must be set to the same value (enabled or
        *     disabled) as Hierarchical Depth Buffer Enable
+       *
+       * The tiled bit must be set. See Section 3DSTATE_DEPTH_BUFFER,
+       * Bit 1.27 "Tiled Surface".
        */
       struct intel_region *region = stencil_irb->mt->region;
 
@@ -290,6 +293,7 @@ static void emit_depthbuffer(struct brw_context *brw)
 	        (1 << 21) | /* separate stencil enable */
 	        (1 << 22) | /* hiz enable */
 	        (BRW_TILEWALK_YMAJOR << 26) |
+	        (1 << 27) | /* tiled surface */
 	        (BRW_SURFACE_2D << 29));
       OUT_BATCH(0);
       OUT_BATCH(((region->width - 1) << 6) |
-- 
1.7.7.1