[Mesa-dev] [PATCH 06/12] radeon: make radeon_texture_image a subclass of swrast_texture_image
Brian Paul
brian.e.paul at gmail.com
Sat Sep 10 10:55:11 PDT 2011
From: Brian Paul <brianp at vmware.com>
---
.../drivers/dri/radeon/radeon_common_context.h | 8 +++++-
src/mesa/drivers/dri/radeon/radeon_mipmap_tree.c | 24 ++++++++--------
src/mesa/drivers/dri/radeon/radeon_tex_copy.c | 12 ++++----
src/mesa/drivers/dri/radeon/radeon_tex_getimage.c | 2 +-
src/mesa/drivers/dri/radeon/radeon_texture.c | 29 +++++++++++--------
5 files changed, 43 insertions(+), 32 deletions(-)
diff --git a/src/mesa/drivers/dri/radeon/radeon_common_context.h b/src/mesa/drivers/dri/radeon/radeon_common_context.h
index 3895ab8..ef39913 100644
--- a/src/mesa/drivers/dri/radeon/radeon_common_context.h
+++ b/src/mesa/drivers/dri/radeon/radeon_common_context.h
@@ -13,6 +13,7 @@
#include "radeon_drm.h"
#include "dri_util.h"
#include "tnl/t_vertex.h"
+#include "swrast/s_context.h"
struct radeon_context;
@@ -174,8 +175,13 @@ struct radeon_hw_state {
/* Texture related */
typedef struct _radeon_texture_image radeon_texture_image;
+
+/**
+ * This is a subclass of swrast_texture_image since we use swrast
+ * for software fallback rendering.
+ */
struct _radeon_texture_image {
- struct gl_texture_image base;
+ struct swrast_texture_image base;
/**
* If mt != 0, the image is stored in hardware format in the
diff --git a/src/mesa/drivers/dri/radeon/radeon_mipmap_tree.c b/src/mesa/drivers/dri/radeon/radeon_mipmap_tree.c
index 03d9b26..f1febd3 100644
--- a/src/mesa/drivers/dri/radeon/radeon_mipmap_tree.c
+++ b/src/mesa/drivers/dri/radeon/radeon_mipmap_tree.c
@@ -448,9 +448,9 @@ static void migrate_image_to_miptree(radeon_mipmap_tree *mt,
assert(image->mt != mt);
assert(dstlvl->valid);
- assert(dstlvl->width == image->base.Width);
- assert(dstlvl->height == image->base.Height);
- assert(dstlvl->depth == image->base.Depth);
+ assert(dstlvl->width == image->base.Base.Width);
+ assert(dstlvl->height == image->base.Base.Height);
+ assert(dstlvl->depth == image->base.Base.Depth);
radeon_print(RADEON_TEXTURE, RADEON_VERBOSE,
"%s miptree %p, image %p, face %d, level %d.\n",
@@ -464,7 +464,7 @@ static void migrate_image_to_miptree(radeon_mipmap_tree *mt,
* In fact, that memcpy() could be done by the hardware in many
* cases, provided that we have a proper memory manager.
*/
- assert(mt->mesaFormat == image->base.TexFormat);
+ assert(mt->mesaFormat == image->base.Base.TexFormat);
radeon_mipmap_level *srclvl = &image->mt->levels[image->mtlevel];
@@ -480,27 +480,27 @@ static void migrate_image_to_miptree(radeon_mipmap_tree *mt,
radeon_bo_unmap(image->mt->bo);
radeon_miptree_unreference(&image->mt);
- } else if (image->base.Data) {
+ } else if (image->base.Base.Data) {
/* This condition should be removed, it's here to workaround
* a segfault when mapping textures during software fallbacks.
*/
radeon_print(RADEON_FALLBACKS, RADEON_IMPORTANT,
"%s Trying to map texture in sowftware fallback.\n",
__func__);
- const uint32_t srcrowstride = _mesa_format_row_stride(image->base.TexFormat, image->base.Width);
- uint32_t rows = image->base.Height * image->base.Depth;
+ const uint32_t srcrowstride = _mesa_format_row_stride(image->base.Base.TexFormat, image->base.Base.Width);
+ uint32_t rows = image->base.Base.Height * image->base.Base.Depth;
- if (_mesa_is_format_compressed(image->base.TexFormat)) {
+ if (_mesa_is_format_compressed(image->base.Base.TexFormat)) {
uint32_t blockWidth, blockHeight;
- _mesa_get_format_block_size(image->base.TexFormat, &blockWidth, &blockHeight);
+ _mesa_get_format_block_size(image->base.Base.TexFormat, &blockWidth, &blockHeight);
rows = (rows + blockHeight - 1) / blockHeight;
}
- copy_rows(dest, dstlvl->rowstride, image->base.Data, srcrowstride,
+ copy_rows(dest, dstlvl->rowstride, image->base.Base.Data, srcrowstride,
rows, srcrowstride);
- _mesa_free_texmemory(image->base.Data);
- image->base.Data = 0;
+ _mesa_free_texmemory(image->base.Base.Data);
+ image->base.Base.Data = 0;
}
radeon_bo_unmap(mt->bo);
diff --git a/src/mesa/drivers/dri/radeon/radeon_tex_copy.c b/src/mesa/drivers/dri/radeon/radeon_tex_copy.c
index 94ff3c4..47b4180 100644
--- a/src/mesa/drivers/dri/radeon/radeon_tex_copy.c
+++ b/src/mesa/drivers/dri/radeon/radeon_tex_copy.c
@@ -59,7 +59,7 @@ do_copy_texsubimage(struct gl_context *ctx,
return GL_FALSE;
}
- if (_mesa_get_format_bits(timg->base.TexFormat, GL_DEPTH_BITS) > 0) {
+ if (_mesa_get_format_bits(timg->base.Base.TexFormat, GL_DEPTH_BITS) > 0) {
if (ctx->ReadBuffer->_DepthBuffer && ctx->ReadBuffer->_DepthBuffer->Wrapped) {
rrb = radeon_renderbuffer(ctx->ReadBuffer->_DepthBuffer->Wrapped);
} else {
@@ -83,8 +83,8 @@ do_copy_texsubimage(struct gl_context *ctx,
assert(rrb->bo);
assert(timg->mt);
assert(timg->mt->bo);
- assert(timg->base.Width >= dstx + width);
- assert(timg->base.Height >= dsty + height);
+ assert(timg->base.Base.Width >= dstx + width);
+ assert(timg->base.Base.Height >= dsty + height);
intptr_t src_offset = rrb->draw_offset;
intptr_t dst_offset = radeon_miptree_image_offset(timg->mt, _mesa_tex_target_to_face(target), level);
@@ -100,9 +100,9 @@ do_copy_texsubimage(struct gl_context *ctx,
}
src_mesaformat = rrb->base.Format;
- dst_mesaformat = timg->base.TexFormat;
+ dst_mesaformat = timg->base.Base.TexFormat;
src_width = rrb->base.Width;
- dst_width = timg->base.Width;
+ dst_width = timg->base.Base.Width;
src_bpp = _mesa_get_format_bytes(src_mesaformat);
dst_bpp = _mesa_get_format_bytes(dst_mesaformat);
if (!radeon->vtbl.check_blit(dst_mesaformat)) {
@@ -136,7 +136,7 @@ do_copy_texsubimage(struct gl_context *ctx,
src_width, rrb->base.Height, x, y,
timg->mt->bo, dst_offset, dst_mesaformat,
timg->mt->levels[level].rowstride / dst_bpp,
- dst_width, timg->base.Height,
+ dst_width, timg->base.Base.Height,
dstx, dsty, width, height, flip_y);
}
diff --git a/src/mesa/drivers/dri/radeon/radeon_tex_getimage.c b/src/mesa/drivers/dri/radeon/radeon_tex_getimage.c
index 4a73089..6e9772e 100644
--- a/src/mesa/drivers/dri/radeon/radeon_tex_getimage.c
+++ b/src/mesa/drivers/dri/radeon/radeon_tex_getimage.c
@@ -64,7 +64,7 @@ radeon_get_tex_image(struct gl_context * ctx, GLenum target, GLint level,
radeon_teximage_map(image, GL_FALSE);
} else {
/* Image hasn't been uploaded to a miptree yet */
- assert(image->base.Data);
+ assert(image->base.Base.Data);
}
if (compressed) {
diff --git a/src/mesa/drivers/dri/radeon/radeon_texture.c b/src/mesa/drivers/dri/radeon/radeon_texture.c
index 182f444..bb27629 100644
--- a/src/mesa/drivers/dri/radeon/radeon_texture.c
+++ b/src/mesa/drivers/dri/radeon/radeon_texture.c
@@ -83,13 +83,18 @@ struct gl_texture_image *radeonNewTextureImage(struct gl_context *ctx)
return CALLOC(sizeof(radeon_texture_image));
}
+
+/**
+ * Delete a texture image object.
+ */
static void
-radeonDeleteTextureImage(struct gl_context * ctx, struct gl_texture_image *img)
+radeonDeleteTextureImage(struct gl_context *ctx, struct gl_texture_image *img)
{
- /* nothing special (yet) for radeon_texture_image */
- _mesa_delete_texture_image(ctx, img);
+ /* nothing special (yet) for radeon_texture_image */
+ _mesa_delete_texture_image(ctx, img);
}
+
/**
* Free memory associated with this texture image.
*/
@@ -99,7 +104,7 @@ void radeonFreeTextureImageBuffer(struct gl_context *ctx, struct gl_texture_imag
if (image->mt) {
radeon_miptree_unreference(&image->mt);
- assert(!image->base.Data);
+ assert(!image->base.Base.Data);
} else {
_mesa_free_texture_image_data(ctx, timage);
}
@@ -127,8 +132,8 @@ static void teximage_set_map_data(radeon_texture_image *image)
lvl = &image->mt->levels[image->mtlevel];
- image->base.Data = image->mt->bo->ptr + lvl->faces[image->mtface].offset;
- image->base.RowStride = lvl->rowstride / _mesa_get_format_bytes(image->base.TexFormat);
+ image->base.Base.Data = image->mt->bo->ptr + lvl->faces[image->mtface].offset;
+ image->base.Base.RowStride = lvl->rowstride / _mesa_get_format_bytes(image->base.Base.TexFormat);
}
@@ -142,7 +147,7 @@ void radeon_teximage_map(radeon_texture_image *image, GLboolean write_enable)
__func__, image,
write_enable ? "true": "false");
if (image->mt) {
- assert(!image->base.Data);
+ assert(!image->base.Base.Data);
radeon_bo_map(image->mt->bo, write_enable);
teximage_set_map_data(image);
@@ -156,9 +161,9 @@ void radeon_teximage_unmap(radeon_texture_image *image)
"%s(img %p)\n",
__func__, image);
if (image->mt) {
- assert(image->base.Data);
+ assert(image->base.Base.Data);
- image->base.Data = 0;
+ image->base.Base.Data = 0;
radeon_bo_unmap(image->mt->bo);
}
}
@@ -169,7 +174,7 @@ static void map_override(struct gl_context *ctx, radeonTexObj *t)
radeon_bo_map(t->bo, GL_FALSE);
- img->base.Data = t->bo->ptr;
+ img->base.Base.Data = t->bo->ptr;
}
static void unmap_override(struct gl_context *ctx, radeonTexObj *t)
@@ -178,7 +183,7 @@ static void unmap_override(struct gl_context *ctx, radeonTexObj *t)
radeon_bo_unmap(t->bo);
- img->base.Data = NULL;
+ img->base.Base.Data = NULL;
}
/**
@@ -1158,7 +1163,7 @@ void radeon_image_target_texture_2d(struct gl_context *ctx, GLenum target,
radeon_bo_ref(image->bo);
t->mt->bo = image->bo;
- if (!radeon_miptree_matches_image(t->mt, &radeonImage->base,
+ if (!radeon_miptree_matches_image(t->mt, &radeonImage->base.Base,
radeonImage->mtface, 0))
fprintf(stderr, "miptree doesn't match image\n");
}
--
1.7.3.4
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