[Mesa-dev] [PATCH 5/6] radeonsi: fix TEX writemask

[Michel Dänzer]

On Don, 2012-08-02 at 11:57 +0200, Christian König wrote: 
> On 02.08.2012 11:46, Michel Dänzer wrote:
> > On Don, 2012-08-02 at 11:33 +0200, Christian König wrote:
> >> On 02.08.2012 11:21, Michel Dänzer wrote:
> >>> On Don, 2012-08-02 at 11:05 +0200, Christian König wrote:
> >>>> On 02.08.2012 07:51, Michel Dänzer wrote:
> >>>>> Couldn't this incorrectly clobber components of the destination which
> >>>>> were supposed to be masked?
> >>>> No cause it is just an optimization of not fetching unwanted components,
> >>>> and not masking anything.
> >>> Hmm, but can't it happen that LLVM assigns destination GPRs containing
> >>> previous values that need to be preserved according to the TGSI
> >>> writemask?
> >> Not currently, as far as I can see, in opposition to the R600 target it
> >> always seems to allocate a new set of 4 registers and then picks the
> >> elements we wanted for the writemask separately.
> > Okay, thanks.
> Does I have your Reviewed-by for this patch also and can push that stuff?

Sure, go ahead.


-- 
Earthling Michel Dänzer           |                   http://www.amd.com
Libre software enthusiast         |          Debian, X and DRI developer