[Mesa-dev] [PATCH 0/8] i965/msaa: Implement 8x MSAA for Gen7 (Ivy Bridge)
stereotype441 at gmail.com
Wed Jul 18 09:20:58 PDT 2012
This patch series enables 8x MSAA for Intel Gen7 (Ivy Bridge) hardware.
Patches 1-4 modify the blorp engine to properly handle 8x MSAA. The
most complex change is in patch 4, which teaches the blorp engine to
understand the layout of 8x IMS MSAA buffers. Unfortunately the code
to interleave and de-interleave IMS buffers is one of the trickiest
parts of blorp (lots of fiddly bit shifts). Fortunately the layout is
pretty similar to the layout of 4x IMS MSAA buffers, so hopefully this
modification shouldn't be too difficult to follow.
Patches 5-6 set up the 3DSTATE_MULTISAMPLE and 3DSTATE_SAMPLE_MASK
command packets properly for 8x MSAA.
Patch 7 ensures that the MCS buffer is allocated with the proper size
for 8x MSAA (it needs to be 32 bits per pixel instead of 8).
Finally, patch 8 enables 8x MSAA for Gen7, by modifying
quantize_num_samples() to handle requests for more than 4 samples, and
by changing ctx->Const.MaxSamples to 8 so that client programs know
they can request 8x MSAA.
This patch series depends on two previous patch series that are still
- [PATCH 0/7] i965/blorp: Improvements to the blorp engine for Gen7
- [PATCH 00/10] i965/msaa: several small fixups.
To see the patch series in the proper context, please fetch from
branch "msaa-8x" on git://github.com/stereotype441/mesa.git.
[PATCH 1/8] i965/blorp: Parameterize manual_blend() by num_samples.
[PATCH 2/8] i965/blorp: Properly adjust primitive size for 8x MSAA.
[PATCH 3/8] i965/blorp: Compute sample number correctly for 8x MSAA.
[PATCH 4/8] i965/blorp: Encode and decode IMS format for 8x MSAA correctly.
[PATCH 5/8] i965/msaa: Adjust 3DSTATE_MULTISAMPLE packet for 8x MSAA.
[PATCH 6/8] i965/msaa: Remove assertion in 3DSTATE_SAMPLE_MASK to allow 8x MSAA.
[PATCH 7/8] i965/msaa: Adjust MCS buffer allocation for 8x MSAA.
[PATCH 8/8] i965/msaa: Switch on 8x MSAA for Gen7.
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