[Mesa-dev] [PATCH 05/15] i965/blorp: Factor gen6_blorp_emit_batch_head into separate functions.

Kenneth Graunke kenneth at whitecape.org
Tue May 22 11:22:36 PDT 2012


On 05/11/2012 11:03 AM, Paul Berry wrote:
> This patch separates out the portions of gen6_blorp_emit_batch_head()
> that emit 3DSTATE_MULTISAMPLE, 3DSTATE_SAMPLE_MASK, and
> STATE_BASE_ADDRESS.  This paves the way for making the blorp code work
> on Gen7, where additional command packets
> (3DSTATE_PUSH_CONSTANT_ALLOC_VS and 3DSTATE_PUSH_CONSTANT_ALLOC_PS)
> need to be emitted before 3DSTATE_MULTISAMPLE.
> ---
>   src/mesa/drivers/dri/i965/brw_blorp.h    |    4 ++
>   src/mesa/drivers/dri/i965/gen6_blorp.cpp |   76 ++++++++++++++++-------------
>   src/mesa/drivers/dri/i965/gen7_blorp.cpp |    3 +
>   3 files changed, 49 insertions(+), 34 deletions(-)
>
> diff --git a/src/mesa/drivers/dri/i965/brw_blorp.h b/src/mesa/drivers/dri/i965/brw_blorp.h
> index b911356..8dabf2c 100644
> --- a/src/mesa/drivers/dri/i965/brw_blorp.h
> +++ b/src/mesa/drivers/dri/i965/brw_blorp.h
> @@ -268,6 +268,10 @@ gen6_blorp_emit_batch_head(struct brw_context *brw,
>                              const brw_blorp_params *params);
>
>   void
> +gen6_blorp_emit_state_base_address(struct brw_context *brw,
> +                                   const brw_blorp_params *params);
> +
> +void
>   gen6_blorp_emit_vertices(struct brw_context *brw,
>                            const brw_blorp_params *params);
>
> diff --git a/src/mesa/drivers/dri/i965/gen6_blorp.cpp b/src/mesa/drivers/dri/i965/gen6_blorp.cpp
> index 85a8ee6..676c92d 100644
> --- a/src/mesa/drivers/dri/i965/gen6_blorp.cpp
> +++ b/src/mesa/drivers/dri/i965/gen6_blorp.cpp
> @@ -99,45 +99,50 @@ gen6_blorp_emit_batch_head(struct brw_context *brw,
>         OUT_BATCH(brw->CMD_PIPELINE_SELECT<<  16);
>         ADVANCE_BATCH();
>      }
> +}
>
> -   gen6_emit_3dstate_multisample(brw, params->num_samples);
> -   gen6_emit_3dstate_sample_mask(brw, params->num_samples);
>
> -   /* CMD_STATE_BASE_ADDRESS
> -    *
> -    * From the Sandy Bridge PRM, Volume 1, Part 1, Table STATE_BASE_ADDRESS:
> -    *     The following commands must be reissued following any change to the
> -    *     base addresses:
> -    *         3DSTATE_CC_POINTERS
> -    *         3DSTATE_BINDING_TABLE_POINTERS
> -    *         3DSTATE_SAMPLER_STATE_POINTERS
> -    *         3DSTATE_VIEWPORT_STATE_POINTERS
> -    *         MEDIA_STATE_POINTERS
> -    */
> -   {
> -      BEGIN_BATCH(10);
> -      OUT_BATCH(CMD_STATE_BASE_ADDRESS<<  16 | (10 - 2));
> -      OUT_BATCH(1); /* GeneralStateBaseAddressModifyEnable */
> -      /* SurfaceStateBaseAddress */
> -      OUT_RELOC(intel->batch.bo, I915_GEM_DOMAIN_SAMPLER, 0, 1);
> -      /* DynamicStateBaseAddress */
> -      OUT_RELOC(intel->batch.bo, (I915_GEM_DOMAIN_RENDER |
> -                                  I915_GEM_DOMAIN_INSTRUCTION), 0, 1);
> -      OUT_BATCH(1); /* IndirectObjectBaseAddress */
> -      if (params->use_wm_prog) {
> -         OUT_RELOC(brw->cache.bo, I915_GEM_DOMAIN_INSTRUCTION, 0,
> -                   1); /* Instruction base address: shader kernels */
> -      } else {
> -         OUT_BATCH(1); /* InstructionBaseAddress */
> -      }
> -      OUT_BATCH(1); /* GeneralStateUpperBound */
> -      OUT_BATCH(1); /* DynamicStateUpperBound */

I don't think you should change this patch (as it's a pure refactor), 
but it's probably best to use:

       OUT_BATCH(0xfffff001);

for the Dynamic State Upper Bound.  We know texture border color is 
broken without this set (it treats the upper bound as 0 rather than 
ignoring it, so all accesses get smashed to the range [base, base + 
0])...other things may be broken too.

I would do that in a new patch.  For this and the new patch:
Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>

> -      OUT_BATCH(1); /* IndirectObjectUpperBound*/
> -      OUT_BATCH(1); /* InstructionAccessUpperBound */
> -      ADVANCE_BATCH();
> +/**
> + * CMD_STATE_BASE_ADDRESS
> + *
> + * From the Sandy Bridge PRM, Volume 1, Part 1, Table STATE_BASE_ADDRESS:
> + *     The following commands must be reissued following any change to the
> + *     base addresses:
> + *         3DSTATE_CC_POINTERS
> + *         3DSTATE_BINDING_TABLE_POINTERS
> + *         3DSTATE_SAMPLER_STATE_POINTERS
> + *         3DSTATE_VIEWPORT_STATE_POINTERS
> + *         MEDIA_STATE_POINTERS
> + */
> +void
> +gen6_blorp_emit_state_base_address(struct brw_context *brw,
> +                                   const brw_blorp_params *params)
> +{
> +   struct intel_context *intel =&brw->intel;
> +
> +   BEGIN_BATCH(10);
> +   OUT_BATCH(CMD_STATE_BASE_ADDRESS<<  16 | (10 - 2));
> +   OUT_BATCH(1); /* GeneralStateBaseAddressModifyEnable */
> +   /* SurfaceStateBaseAddress */
> +   OUT_RELOC(intel->batch.bo, I915_GEM_DOMAIN_SAMPLER, 0, 1);
> +   /* DynamicStateBaseAddress */
> +   OUT_RELOC(intel->batch.bo, (I915_GEM_DOMAIN_RENDER |
> +                               I915_GEM_DOMAIN_INSTRUCTION), 0, 1);
> +   OUT_BATCH(1); /* IndirectObjectBaseAddress */
> +   if (params->use_wm_prog) {
> +      OUT_RELOC(brw->cache.bo, I915_GEM_DOMAIN_INSTRUCTION, 0,
> +                1); /* Instruction base address: shader kernels */
> +   } else {
> +      OUT_BATCH(1); /* InstructionBaseAddress */
>      }
> +   OUT_BATCH(1); /* GeneralStateUpperBound */
> +   OUT_BATCH(1); /* DynamicStateUpperBound */
> +   OUT_BATCH(1); /* IndirectObjectUpperBound*/
> +   OUT_BATCH(1); /* InstructionAccessUpperBound */
> +   ADVANCE_BATCH();
>   }
>
> +
>   void
>   gen6_blorp_emit_vertices(struct brw_context *brw,
>                            const brw_blorp_params *params)
> @@ -1009,6 +1014,9 @@ gen6_blorp_exec(struct intel_context *intel,
>
>      uint32_t prog_offset = params->get_wm_prog(brw,&prog_data);
>      gen6_blorp_emit_batch_head(brw, params);
> +   gen6_emit_3dstate_multisample(brw, params->num_samples);
> +   gen6_emit_3dstate_sample_mask(brw, params->num_samples);
> +   gen6_blorp_emit_state_base_address(brw, params);
>      gen6_blorp_emit_vertices(brw, params);
>      gen6_blorp_emit_urb_config(brw, params);
>      if (params->use_wm_prog) {
> diff --git a/src/mesa/drivers/dri/i965/gen7_blorp.cpp b/src/mesa/drivers/dri/i965/gen7_blorp.cpp
> index e5b27dd..7573b47 100644
> --- a/src/mesa/drivers/dri/i965/gen7_blorp.cpp
> +++ b/src/mesa/drivers/dri/i965/gen7_blorp.cpp
> @@ -725,6 +725,9 @@ gen7_blorp_exec(struct intel_context *intel,
>
>      uint32_t prog_offset = params->get_wm_prog(brw,&prog_data);
>      gen6_blorp_emit_batch_head(brw, params);
> +   gen6_emit_3dstate_multisample(brw, params->num_samples);
> +   gen6_emit_3dstate_sample_mask(brw, params->num_samples);
> +   gen6_blorp_emit_state_base_address(brw, params);
>      gen6_blorp_emit_vertices(brw, params);
>      gen7_blorp_emit_urb_config(brw, params);
>      if (params->use_wm_prog) {



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