[Mesa-dev] [PATCH 2/3] i965/gen7: Set MOCS L3 cacheability for IVB/BYT

Ville Syrjälä ville.syrjala at linux.intel.com
Wed Aug 14 00:50:36 PDT 2013


On Wed, Aug 14, 2013 at 10:45:23AM +0300, Ville Syrjälä wrote:
> On Tue, Aug 13, 2013 at 05:46:55PM -0700, Chad Versace wrote:
> > On 08/13/2013 03:31 PM, Vedran Rodic wrote:
> > > On Mon, Aug 12, 2013 at 3:07 PM,  <ville.syrjala at linux.intel.com> wrote:
> > >> From: Ville Syrjälä <ville.syrjala at linux.intel.com>
> > >>
> > >> IVB/BYT also has the same L3 cacheability control in MOCS as HSW,
> > >> so let's make use of it.
> > >
> > > According to the discussion we had on #intel-gfx a few weeks ago, on
> > > IVB all Mesa memory is already marked as cached in DRM allocated PTEs.
> > > So this should not have any effect. Or I'm misunderstanding something.
> > >
> > > As I understand, marking everything uncacheable and then marking just
> > > certain things cacheable could make a difference (since AFAIK, you
> > > can't mark select regions as uncacheable after you mark PTEs as
> > > cacheable on IVB).
> > >
> > > Can somebody more knowledgeable comment?
> > 
> > On Ivybridge, the PTEs mark only contexts as LLC+L3 cacheable. Everything
> > else is marked as cacheable in LLC, but not L3. So, Ville's patches will
> > give a perf boost to Mesa running on any kernel that continues that cacheing
> > policy.
> 
> There's a bit more to that story.
> 
> For L3 cacheability, IVB won't consult the PTE for anything that has a
> relevant MOCS field. So even if you make everything L3 cacheable through
> the PTEs, MOCS will always override it. How do i know you ask? Well,
> BSpec says so for one, and more importantly I verified this by running
> some tests on a patched kernel that makes all currently LLC cacheable
> PTEs LLC+L3 cacheable. The patched kernel had similar performance
> numbers as the unpatched kernel, and the MOCS patches had the same
> effect on both kernels.
> 
> According to BSpec there are certain things that don't have a MOCS field,
> so in theory the L3 PTE setting should have some effect, but for the
> (mostly) gaming benchmarks I ran there didn't seem to be a significant
> difference.
> 
> For LLC cachebility the story will be different because there IVB MOCS
> can only say "LLC cacheable" or "consult the PTE". So to make stuff
> uncached in LLC on IVB, we'd need to issues the set_caching ioctl to
> change the PTE to uncached, and after that we could use just the MOCS
> to select the LLC caching policy. Since the set_caching ioctl only needs
> to be issued once per object (or you could use the , there 

Sorry hit send by accident. Was going to say we could use the new
create2 ioctl Chris has proposed that allows you to set the cache mode
when creating the object. So there won't be a performance hit from
extra ioctls getting issued all the time.

-- 
Ville Syrjälä
Intel OTC


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