[Mesa-dev] [PATCH 16/30] i965/gs: Add GS_OPCODE_SET_WRITE_OFFSET.

[Paul Berry]

On 20 August 2013 11:30, Paul Berry <stereotype441 at gmail.com> wrote:

> ---
>  src/mesa/drivers/dri/i965/brw_defines.h     | 16 ++++++++++++++++
>  src/mesa/drivers/dri/i965/brw_shader.cpp    |  2 ++
>  src/mesa/drivers/dri/i965/brw_vec4.h        |  3 +++
>  src/mesa/drivers/dri/i965/brw_vec4_emit.cpp | 18 ++++++++++++++++++
>  4 files changed, 39 insertions(+)
>
> diff --git a/src/mesa/drivers/dri/i965/brw_defines.h
> b/src/mesa/drivers/dri/i965/brw_defines.h
> index 52009e2..ff270da 100644
> --- a/src/mesa/drivers/dri/i965/brw_defines.h
> +++ b/src/mesa/drivers/dri/i965/brw_defines.h
> @@ -817,6 +817,22 @@ enum opcode {
>      * for Slot {0,1}" fields in the message header.
>      */
>     GS_OPCODE_THREAD_END,
> +
> +   /**
> +    * Set the "Slot {0,1} Offset" fields of a URB_WRITE message header.
> +    *
> +    * - dst is the MRF containing the message header.
> +    *
> +    * - src0.x indicates which portion of the URB should be written to
> (e.g. a
> +    *   vertex number)
> +    *
> +    * - src1 is an immediate multiplier which will be applied to src0
> +    *   (e.g. the size of a single vertex in the URB).
> +    *
> +    * Note: the hardware will apply this offset *in addition to* the
> offset in
> +    * vec4_instruction::offset.
> +    */
> +   GS_OPCODE_SET_WRITE_OFFSET,
>  };
>
>  #define BRW_PREDICATE_NONE             0
> diff --git a/src/mesa/drivers/dri/i965/brw_shader.cpp
> b/src/mesa/drivers/dri/i965/brw_shader.cpp
> index 689e908..e5d939a 100644
> --- a/src/mesa/drivers/dri/i965/brw_shader.cpp
> +++ b/src/mesa/drivers/dri/i965/brw_shader.cpp
> @@ -501,6 +501,8 @@ brw_instruction_name(enum opcode op)
>        return "gs_urb_write";
>     case GS_OPCODE_THREAD_END:
>        return "gs_thread_end";
> +   case GS_OPCODE_SET_WRITE_OFFSET:
> +      return "set_write_offset";
>
>     default:
>        /* Yes, this leaks.  It's in debug code, it should never occur, and
> if
> diff --git a/src/mesa/drivers/dri/i965/brw_vec4.h
> b/src/mesa/drivers/dri/i965/brw_vec4.h
> index a95f61f..484e578 100644
> --- a/src/mesa/drivers/dri/i965/brw_vec4.h
> +++ b/src/mesa/drivers/dri/i965/brw_vec4.h
> @@ -630,6 +630,9 @@ private:
>     void generate_vs_urb_write(vec4_instruction *inst);
>     void generate_gs_urb_write(vec4_instruction *inst);
>     void generate_gs_thread_end(vec4_instruction *inst);
> +   void generate_gs_set_write_offset(struct brw_reg dst,
> +                                     struct brw_reg src0,
> +                                     struct brw_reg src1);
>     void generate_oword_dual_block_offsets(struct brw_reg m1,
>                                           struct brw_reg index);
>     void generate_scratch_write(vec4_instruction *inst,
> diff --git a/src/mesa/drivers/dri/i965/brw_vec4_emit.cpp
> b/src/mesa/drivers/dri/i965/brw_vec4_emit.cpp
> index 19ed358..85ad339 100644
> --- a/src/mesa/drivers/dri/i965/brw_vec4_emit.cpp
> +++ b/src/mesa/drivers/dri/i965/brw_vec4_emit.cpp
> @@ -443,6 +443,20 @@
> vec4_generator::generate_gs_thread_end(vec4_instruction *inst)
>  }
>
>  void
> +vec4_generator::generate_gs_set_write_offset(struct brw_reg dst,
> +                                             struct brw_reg src0,
> +                                             struct brw_reg src1)
> +{
> +   brw_push_insn_state(p);
> +   brw_set_access_mode(p, BRW_ALIGN_1);
> +   brw_set_mask_control(p, BRW_MASK_DISABLE);
> +   brw_MUL(p, suboffset(stride(dst, 2, 2, 1), 3), stride(src0, 8, 2, 4),
> +           src1);
>

>From our in-person code review yesterday:

Comments are needed to explain why I chose the strides I did.  These
comments should refer to the PRM documentation of the message header.


> +   brw_set_access_mode(p, BRW_ALIGN_16);
> +   brw_pop_insn_state(p);
> +}
> +
> +void
>  vec4_generator::generate_oword_dual_block_offsets(struct brw_reg m1,
>                                                    struct brw_reg index)
>  {
> @@ -918,6 +932,10 @@
> vec4_generator::generate_vec4_instruction(vec4_instruction *instruction,
>        generate_gs_thread_end(inst);
>        break;
>
> +   case GS_OPCODE_SET_WRITE_OFFSET:
> +      generate_gs_set_write_offset(dst, src[0], src[1]);
> +      break;
> +
>     case SHADER_OPCODE_SHADER_TIME_ADD:
>        brw_shader_time_add(p, src[0], SURF_INDEX_VS_SHADER_TIME);
>        mark_surface_used(SURF_INDEX_VS_SHADER_TIME);
> --
> 1.8.3.4
>
>
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