[Mesa-dev] [PATCH] R600/SI: Make sure M0 is loaded for V_INTERP_MOV_F32

[Tom Stellard]

On Wed, Feb 20, 2013 at 12:13:43PM +0100, Michel Dänzer wrote:
> From: Michel Dänzer <michel.daenzer at amd.com>
> 
> NOTE: This is a candidate for the Mesa stable branch.
> 
> Signed-off-by: Michel Dänzer <michel.daenzer at amd.com>
Reviewed-by: Tom Stellard <thomas.stellard at amd.com>
> ---
> 
> Not sure why the lack of this didn't seem to cause problems in my testing
> last week...
> 
>  lib/Target/R600/SIInstructions.td               |  3 ++-
>  test/CodeGen/R600/llvm.SI.fs.interp.constant.ll | 23 +++++++++++++++++++++++
>  2 files changed, 25 insertions(+), 1 deletion(-)
>  create mode 100644 test/CodeGen/R600/llvm.SI.fs.interp.constant.ll
> 
> diff --git a/lib/Target/R600/SIInstructions.td b/lib/Target/R600/SIInstructions.td
> index b4a263d..aef239c 100644
> --- a/lib/Target/R600/SIInstructions.td
> +++ b/lib/Target/R600/SIInstructions.td
> @@ -1311,7 +1311,8 @@ def : Pat <
>  
>  def : Pat <
>    (int_SI_fs_interp_constant imm:$attr_chan, imm:$attr, SReg_32:$params),
> -  (V_INTERP_MOV_F32 INTERP.P0, imm:$attr_chan, imm:$attr, SReg_32:$params)
> +  (V_INTERP_MOV_F32 INTERP.P0, imm:$attr_chan, imm:$attr,
> +                    (S_MOV_B32 SReg_32:$params))
>  >;
>  
>  def : Pat <
> diff --git a/test/CodeGen/R600/llvm.SI.fs.interp.constant.ll b/test/CodeGen/R600/llvm.SI.fs.interp.constant.ll
> new file mode 100644
> index 0000000..0c19f14
> --- /dev/null
> +++ b/test/CodeGen/R600/llvm.SI.fs.interp.constant.ll
> @@ -0,0 +1,23 @@
> +;RUN: llc < %s -march=r600 -mcpu=SI | FileCheck %s
> +
> +;CHECK: S_MOV_B32
> +;CHECK-NEXT: V_INTERP_MOV_F32
> +
> +define void @main() {
> +main_body:
> +  call void @llvm.AMDGPU.shader.type(i32 0)
> +  %0 = load i32 addrspace(8)* inttoptr (i32 6 to i32 addrspace(8)*)
> +  %1 = call float @llvm.SI.fs.interp.constant(i32 0, i32 0, i32 %0)
> +  %2 = call i32 @llvm.SI.packf16(float %1, float %1)
> +  %3 = bitcast i32 %2 to float
> +  call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 1, float %3, float %3, float %3, float %3)
> +  ret void
> +}
> +
> +declare void @llvm.AMDGPU.shader.type(i32)
> +
> +declare float @llvm.SI.fs.interp.constant(i32, i32, i32) readonly
> +
> +declare i32 @llvm.SI.packf16(float, float) readnone
> +
> +declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)
> -- 
> 1.8.1.3
> 
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