[Mesa-dev] [PATCH 2/3] i965: Emit the CC state pointer directly rather than via atoms.
Kenneth Graunke
kenneth at whitecape.org
Mon Jun 10 13:12:33 PDT 2013
See the previous commit for the rationale.
Signed-off-by: Kenneth Graunke <kenneth at whitecape.org>
---
src/mesa/drivers/dri/i965/brw_context.h | 2 --
src/mesa/drivers/dri/i965/brw_state.h | 1 -
src/mesa/drivers/dri/i965/brw_state_upload.c | 2 --
src/mesa/drivers/dri/i965/gen6_cc.c | 23 ++++++++++++++++++-----
src/mesa/drivers/dri/i965/gen7_cc_state.c | 20 --------------------
5 files changed, 18 insertions(+), 30 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_context.h b/src/mesa/drivers/dri/i965/brw_context.h
index 0e3b2ab..2150e67 100644
--- a/src/mesa/drivers/dri/i965/brw_context.h
+++ b/src/mesa/drivers/dri/i965/brw_context.h
@@ -607,7 +607,6 @@ struct brw_vs_prog_data {
enum brw_cache_id {
BRW_DEPTH_STENCIL_STATE,
- BRW_COLOR_CALC_STATE,
BRW_CC_VP,
BRW_CC_UNIT,
BRW_WM_PROG,
@@ -701,7 +700,6 @@ enum shader_time_shader_type {
/* Flags for brw->state.cache.
*/
#define CACHE_NEW_DEPTH_STENCIL_STATE (1<<BRW_DEPTH_STENCIL_STATE)
-#define CACHE_NEW_COLOR_CALC_STATE (1<<BRW_COLOR_CALC_STATE)
#define CACHE_NEW_CC_VP (1<<BRW_CC_VP)
#define CACHE_NEW_CC_UNIT (1<<BRW_CC_UNIT)
#define CACHE_NEW_WM_PROG (1<<BRW_WM_PROG)
diff --git a/src/mesa/drivers/dri/i965/brw_state.h b/src/mesa/drivers/dri/i965/brw_state.h
index aee4b67..211fb28 100644
--- a/src/mesa/drivers/dri/i965/brw_state.h
+++ b/src/mesa/drivers/dri/i965/brw_state.h
@@ -106,7 +106,6 @@ extern const struct brw_tracked_state gen6_vs_state;
extern const struct brw_tracked_state gen6_wm_push_constants;
extern const struct brw_tracked_state gen6_wm_state;
extern const struct brw_tracked_state gen7_depthbuffer;
-extern const struct brw_tracked_state gen7_cc_state_pointer;
extern const struct brw_tracked_state gen7_cc_viewport_state_pointer;
extern const struct brw_tracked_state gen7_clip_state;
extern const struct brw_tracked_state gen7_depth_stencil_state_pointer;
diff --git a/src/mesa/drivers/dri/i965/brw_state_upload.c b/src/mesa/drivers/dri/i965/brw_state_upload.c
index e3a097f..99680fd 100644
--- a/src/mesa/drivers/dri/i965/brw_state_upload.c
+++ b/src/mesa/drivers/dri/i965/brw_state_upload.c
@@ -188,7 +188,6 @@ static const struct brw_tracked_state *gen7_atoms[] =
&gen6_blend_state, /* must do before cc unit */
&gen6_color_calc_state, /* must do before cc unit */
&gen6_depth_stencil_state, /* must do before cc unit */
- &gen7_cc_state_pointer,
&gen7_depth_stencil_state_pointer,
&gen6_vs_push_constants, /* Before vs_state */
@@ -394,7 +393,6 @@ static struct dirty_bit_map brw_bits[] = {
static struct dirty_bit_map cache_bits[] = {
DEFINE_BIT(CACHE_NEW_DEPTH_STENCIL_STATE),
- DEFINE_BIT(CACHE_NEW_COLOR_CALC_STATE),
DEFINE_BIT(CACHE_NEW_CC_VP),
DEFINE_BIT(CACHE_NEW_CC_UNIT),
DEFINE_BIT(CACHE_NEW_WM_PROG),
diff --git a/src/mesa/drivers/dri/i965/gen6_cc.c b/src/mesa/drivers/dri/i965/gen6_cc.c
index 466ef43..ef0f62d 100644
--- a/src/mesa/drivers/dri/i965/gen6_cc.c
+++ b/src/mesa/drivers/dri/i965/gen6_cc.c
@@ -255,6 +255,7 @@ static void
gen6_upload_color_calc_state(struct brw_context *brw)
{
struct gl_context *ctx = &brw->intel.ctx;
+ struct intel_context *intel = &brw->intel;
struct gen6_color_calc_state *cc;
cc = brw_state_batch(brw, AUB_TRACE_CC_STATE,
@@ -275,13 +276,26 @@ gen6_upload_color_calc_state(struct brw_context *brw)
cc->constant_b = ctx->Color.BlendColorUnclamped[2];
cc->constant_a = ctx->Color.BlendColorUnclamped[3];
- brw->state.dirty.cache |= CACHE_NEW_COLOR_CALC_STATE;
+ /* Point the GPU at the new indirect state. */
+ if (intel->gen == 6) {
+ BEGIN_BATCH(4);
+ OUT_BATCH(_3DSTATE_CC_STATE_POINTERS << 16 | (4 - 2));
+ OUT_BATCH(0);
+ OUT_BATCH(0);
+ OUT_BATCH(brw->cc.state_offset | 1);
+ ADVANCE_BATCH();
+ } else {
+ BEGIN_BATCH(2);
+ OUT_BATCH(_3DSTATE_CC_STATE_POINTERS << 16 | (2 - 2));
+ OUT_BATCH(brw->cc.state_offset | 1);
+ ADVANCE_BATCH();
+ }
}
const struct brw_tracked_state gen6_color_calc_state = {
.dirty = {
.mesa = _NEW_COLOR | _NEW_STENCIL,
- .brw = BRW_NEW_BATCH,
+ .brw = BRW_NEW_BATCH | BRW_NEW_STATE_BASE_ADDRESS,
.cache = 0,
},
.emit = gen6_upload_color_calc_state,
@@ -295,7 +309,7 @@ static void upload_cc_state_pointers(struct brw_context *brw)
OUT_BATCH(_3DSTATE_CC_STATE_POINTERS << 16 | (4 - 2));
OUT_BATCH(0);
OUT_BATCH(brw->cc.depth_stencil_state_offset | 1);
- OUT_BATCH(brw->cc.state_offset | 1);
+ OUT_BATCH(0);
ADVANCE_BATCH();
}
@@ -304,8 +318,7 @@ const struct brw_tracked_state gen6_cc_state_pointers = {
.mesa = 0,
.brw = (BRW_NEW_BATCH |
BRW_NEW_STATE_BASE_ADDRESS),
- .cache = (CACHE_NEW_COLOR_CALC_STATE |
- CACHE_NEW_DEPTH_STENCIL_STATE)
+ .cache = CACHE_NEW_DEPTH_STENCIL_STATE
},
.emit = upload_cc_state_pointers,
};
diff --git a/src/mesa/drivers/dri/i965/gen7_cc_state.c b/src/mesa/drivers/dri/i965/gen7_cc_state.c
index 9ad124e..bd0b7d6 100644
--- a/src/mesa/drivers/dri/i965/gen7_cc_state.c
+++ b/src/mesa/drivers/dri/i965/gen7_cc_state.c
@@ -29,26 +29,6 @@
#include "main/macros.h"
static void
-upload_cc_state_pointers(struct brw_context *brw)
-{
- struct intel_context *intel = &brw->intel;
-
- BEGIN_BATCH(2);
- OUT_BATCH(_3DSTATE_CC_STATE_POINTERS << 16 | (2 - 2));
- OUT_BATCH(brw->cc.state_offset | 1);
- ADVANCE_BATCH();
-}
-
-const struct brw_tracked_state gen7_cc_state_pointer = {
- .dirty = {
- .mesa = 0,
- .brw = BRW_NEW_BATCH,
- .cache = CACHE_NEW_COLOR_CALC_STATE
- },
- .emit = upload_cc_state_pointers,
-};
-
-static void
upload_depth_stencil_state_pointer(struct brw_context *brw)
{
struct intel_context *intel = &brw->intel;
--
1.8.3
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