[Mesa-dev] RFC: Haswell resource streamer/hw-generated binding tables (v2)

Abdiel Janulgue abdiel.janulgue at linux.intel.com
Tue Oct 8 14:41:37 PDT 2013


Prerequisites:

  - Kernel patches: [1]
    (do 'make headers_install' and update libdrm headers after compiling
    the kernel)
  - Mesa patch: [2]

This is an update from my previous RFC patches [3]. Most notable 
change is that the resource streamer is an experimental feature 
disabled by default and toggled by setting the env variable 
INTEL_RESOURCE_STREAMER=1.

After struggling for some time with hard-lockups, I found out that
the previous implementation was not too conformant with the specs.
The fixes include:
  
  - Fixed the binding table pool allocation algorithm. Previous
  implementation allocated up to 128k binding table pool but the 
  hardware only allows an offset into the pool entry of up to 64k.

  - Take into consideration the smaller size of a hw-generated binding
  tables. Surface state offsets are expressed as 16 bit entries instead
  of 32.
  
  - Properly update binding table offsets after being triggered by 
  new constant buffers in addition to new surfaces state change.

There are probably still some nasty critters somewhere I failed to
workaround but I did manage to coax Piglit to go thru a successful run,
at least, without hardlocking the machine (tested on Haswell GT3). This
was in part due to Paul's fix on a send instruction complaint by the 
simulator inside blorp [2] which only got triggered for some reason
when the resource streamer is on.

Cc: Paul Berry <stereotype441 at gmail.com>
Cc: Kenneth Graunke <kenneth at whitecape.org>
Cc: Chad Versace <chad.versace at linux.intel.com>
Cc: Eric Anholt <eric at anholt.net>

[PATCH 01/16] i965/gen7.5: Implement resource streamer control
[PATCH 02/16] i965/gen7.5: Introduce INTEL_RESOURCE_STREAMER to
[PATCH 03/16] i965/gen7.5: Pass resource streamer enable flags on
[PATCH 04/16] i965/gen7.5: Temporarily disable resource streamer
[PATCH 05/16] i965/gen7.5: Implement MI_RS_STORE_DATA_IMM workaround
[PATCH 06/16] i965/gen7.5: Enable hardware-generated binding tables
[PATCH 07/16] i965/gen7.5: Enable hardware-generated binding tables
[PATCH 08/16] i965/gen7.5: Skip manual binding table upload
[PATCH 09/16] i965/gen7.5: Implement opcodes for the hw-generated
[PATCH 10/16] i965/gen7.5: Update surface state entries in
[PATCH 11/16] i965/gen7.5: Update surface entries for pull constants
[PATCH 12/16] i965/gen7.5: Update surface state entries for
[PATCH 13/16] i965/gen7.5: Update surface state entries for WM UBO
[PATCH 14/16] i965/gen7.5: Update surface state entry for WM pull
[PATCH 15/16] i965/blorp: Update surface state entries in blorp.
[PATCH 16/16] i965/gen7.5: Flush on-chip binding table to pool

--
[1] http://lists.freedesktop.org/archives/intel-gfx/2013-October/034430.html
[2] http://lists.freedesktop.org/archives/mesa-dev/2013-September/045315.html
[3] http://lists.freedesktop.org/archives/mesa-dev/2013-July/041473.html


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