[Mesa-dev] [PATCH] r600g: pad IBs to a multiple of 4 DWs on r6xx

[Alex Deucher]

IBs need to be a multiple of 4 dwords on r6xx asics
to avoid a hw bug.

Signed-off-by: Alex Deucher <alexander.deucher at amd.com>
CC: "9.2" <mesa-stable at lists.freedesktop.org>
CC: "9.1" <mesa-stable at lists.freedesktop.org>
---
 src/gallium/drivers/r600/r600_hw_context.c | 13 +++++++++++++
 1 file changed, 13 insertions(+)

diff --git a/src/gallium/drivers/r600/r600_hw_context.c b/src/gallium/drivers/r600/r600_hw_context.c
index 97b0f9c..0a219af 100644
--- a/src/gallium/drivers/r600/r600_hw_context.c
+++ b/src/gallium/drivers/r600/r600_hw_context.c
@@ -347,6 +347,19 @@ void r600_context_flush(struct r600_context *ctx, unsigned flags)
 		flags |= RADEON_FLUSH_KEEP_TILING_FLAGS;
 	}
 
+	/* Pad the GFX CS to a multiple of 4 dwords on rv6xx
+	 * to avoid a hw bug.
+	 */
+	if (ctx->chip_class < R700) {
+		unsigned i;
+		unsigned padding_dw = 4 - cs->cdw % 4;
+		if (padding_dw < 4) {
+			for (i = 0; i < padding_dw; i++) {
+				cs->buf[cs->cdw++] = 0x80000000;
+			}
+		}
+	}
+
 	/* Flush the CS. */
 	ctx->ws->cs_flush(ctx->rings.gfx.cs, flags, ctx->screen->cs_count++);
 }
-- 
1.8.3.1