[Mesa-dev] [RFC 19/27] i965/fs: Move emission of ALUs into fs_emitter

Topi Pohjolainen topi.pohjolainen at intel.com
Sat Feb 22 01:05:45 PST 2014


Signed-off-by: Topi Pohjolainen <topi.pohjolainen at intel.com>
---
 src/mesa/drivers/dri/i965/brw_fs.cpp         | 89 ----------------------------
 src/mesa/drivers/dri/i965/brw_fs.h           | 63 ++++++++++----------
 src/mesa/drivers/dri/i965/brw_fs_emitter.cpp | 88 +++++++++++++++++++++++++++
 3 files changed, 120 insertions(+), 120 deletions(-)

diff --git a/src/mesa/drivers/dri/i965/brw_fs.cpp b/src/mesa/drivers/dri/i965/brw_fs.cpp
index 955894c..d600327 100644
--- a/src/mesa/drivers/dri/i965/brw_fs.cpp
+++ b/src/mesa/drivers/dri/i965/brw_fs.cpp
@@ -137,75 +137,6 @@ fs_inst::fs_inst(enum opcode opcode, fs_reg dst,
       assert(src[2].reg_offset >= 0);
 }
 
-#define ALU1(op)                                                        \
-   fs_inst *                                                            \
-   fs_visitor::op(fs_reg dst, fs_reg src0)                              \
-   {                                                                    \
-      return new(mem_ctx) fs_inst(BRW_OPCODE_##op, dst, src0);          \
-   }
-
-#define ALU2(op)                                                        \
-   fs_inst *                                                            \
-   fs_visitor::op(fs_reg dst, fs_reg src0, fs_reg src1)                 \
-   {                                                                    \
-      return new(mem_ctx) fs_inst(BRW_OPCODE_##op, dst, src0, src1);    \
-   }
-
-#define ALU3(op)                                                        \
-   fs_inst *                                                            \
-   fs_visitor::op(fs_reg dst, fs_reg src0, fs_reg src1, fs_reg src2)    \
-   {                                                                    \
-      return new(mem_ctx) fs_inst(BRW_OPCODE_##op, dst, src0, src1, src2);\
-   }
-
-ALU1(NOT)
-ALU1(MOV)
-ALU1(FRC)
-ALU1(RNDD)
-ALU1(RNDE)
-ALU1(RNDZ)
-ALU2(ADD)
-ALU2(MUL)
-ALU2(MACH)
-ALU2(AND)
-ALU2(OR)
-ALU2(XOR)
-ALU2(SHL)
-ALU2(SHR)
-ALU2(ASR)
-ALU3(LRP)
-ALU1(BFREV)
-ALU3(BFE)
-ALU2(BFI1)
-ALU3(BFI2)
-ALU1(FBH)
-ALU1(FBL)
-ALU1(CBIT)
-ALU3(MAD)
-ALU2(ADDC)
-ALU2(SUBB)
-ALU2(SEL)
-
-/** Gen4 predicated IF. */
-fs_inst *
-fs_visitor::IF(uint32_t predicate)
-{
-   fs_inst *inst = new(mem_ctx) fs_inst(BRW_OPCODE_IF);
-   inst->predicate = predicate;
-   return inst;
-}
-
-/** Gen6 IF with embedded comparison. */
-fs_inst *
-fs_visitor::IF(fs_reg src0, fs_reg src1, uint32_t condition)
-{
-   assert(brw->gen == 6);
-   fs_inst *inst = new(mem_ctx) fs_inst(BRW_OPCODE_IF,
-                                        reg_null_d, src0, src1);
-   inst->conditional_mod = condition;
-   return inst;
-}
-
 /**
  * CMP: Sets the low bit of the destination channels with the result
  * of the comparison, while the upper bits are undefined, and updates
@@ -301,26 +232,6 @@ fs_visitor::VARYING_PULL_CONSTANT_LOAD(fs_reg dst, fs_reg surf_index,
    return instructions;
 }
 
-/**
- * A helper for MOV generation for fixing up broken hardware SEND dependency
- * handling.
- */
-fs_inst *
-fs_visitor::DEP_RESOLVE_MOV(int grf)
-{
-   fs_inst *inst = MOV(brw_null_reg(), fs_reg(GRF, grf, BRW_REGISTER_TYPE_F));
-
-   inst->ir = NULL;
-   inst->annotation = "send dependency resolve";
-
-   /* The caller always wants uncompressed to emit the minimal extra
-    * dependencies, and to avoid having to deal with aligning its regs to 2.
-    */
-   inst->force_uncompressed = true;
-
-   return inst;
-}
-
 bool
 fs_inst::equals(fs_inst *inst)
 {
diff --git a/src/mesa/drivers/dri/i965/brw_fs.h b/src/mesa/drivers/dri/i965/brw_fs.h
index abc3666..5b0687e 100644
--- a/src/mesa/drivers/dri/i965/brw_fs.h
+++ b/src/mesa/drivers/dri/i965/brw_fs.h
@@ -247,6 +247,38 @@ protected:
               struct brw_wm_compile *c,
               unsigned dispatch_width);
 
+   fs_inst *MOV(fs_reg dst, fs_reg src);
+   fs_inst *NOT(fs_reg dst, fs_reg src);
+   fs_inst *RNDD(fs_reg dst, fs_reg src);
+   fs_inst *RNDE(fs_reg dst, fs_reg src);
+   fs_inst *RNDZ(fs_reg dst, fs_reg src);
+   fs_inst *FRC(fs_reg dst, fs_reg src);
+   fs_inst *ADD(fs_reg dst, fs_reg src0, fs_reg src1);
+   fs_inst *MUL(fs_reg dst, fs_reg src0, fs_reg src1);
+   fs_inst *MACH(fs_reg dst, fs_reg src0, fs_reg src1);
+   fs_inst *MAC(fs_reg dst, fs_reg src0, fs_reg src1);
+   fs_inst *SHL(fs_reg dst, fs_reg src0, fs_reg src1);
+   fs_inst *SHR(fs_reg dst, fs_reg src0, fs_reg src1);
+   fs_inst *ASR(fs_reg dst, fs_reg src0, fs_reg src1);
+   fs_inst *AND(fs_reg dst, fs_reg src0, fs_reg src1);
+   fs_inst *OR(fs_reg dst, fs_reg src0, fs_reg src1);
+   fs_inst *XOR(fs_reg dst, fs_reg src0, fs_reg src1);
+   fs_inst *IF(uint32_t predicate);
+   fs_inst *IF(fs_reg src0, fs_reg src1, uint32_t condition);
+   fs_inst *LRP(fs_reg dst, fs_reg a, fs_reg y, fs_reg x);
+   fs_inst *DEP_RESOLVE_MOV(int grf);
+   fs_inst *BFREV(fs_reg dst, fs_reg value);
+   fs_inst *BFE(fs_reg dst, fs_reg bits, fs_reg offset, fs_reg value);
+   fs_inst *BFI1(fs_reg dst, fs_reg bits, fs_reg offset);
+   fs_inst *BFI2(fs_reg dst, fs_reg bfi1_dst, fs_reg insert, fs_reg base);
+   fs_inst *FBH(fs_reg dst, fs_reg value);
+   fs_inst *FBL(fs_reg dst, fs_reg value);
+   fs_inst *CBIT(fs_reg dst, fs_reg value);
+   fs_inst *MAD(fs_reg dst, fs_reg c, fs_reg b, fs_reg a);
+   fs_inst *ADDC(fs_reg dst, fs_reg src0, fs_reg src1);
+   fs_inst *SUBB(fs_reg dst, fs_reg src0, fs_reg src1);
+   fs_inst *SEL(fs_reg dst, fs_reg src0, fs_reg src1);
+
    fs_inst *emit(enum opcode opcode);
    fs_inst *emit(enum opcode opcode, fs_reg dst);
    fs_inst *emit(enum opcode opcode, fs_reg dst, fs_reg src0);
@@ -315,39 +347,8 @@ public:
 
    bool can_do_source_mods(fs_inst *inst);
 
-   fs_inst *MOV(fs_reg dst, fs_reg src);
-   fs_inst *NOT(fs_reg dst, fs_reg src);
-   fs_inst *RNDD(fs_reg dst, fs_reg src);
-   fs_inst *RNDE(fs_reg dst, fs_reg src);
-   fs_inst *RNDZ(fs_reg dst, fs_reg src);
-   fs_inst *FRC(fs_reg dst, fs_reg src);
-   fs_inst *ADD(fs_reg dst, fs_reg src0, fs_reg src1);
-   fs_inst *MUL(fs_reg dst, fs_reg src0, fs_reg src1);
-   fs_inst *MACH(fs_reg dst, fs_reg src0, fs_reg src1);
-   fs_inst *MAC(fs_reg dst, fs_reg src0, fs_reg src1);
-   fs_inst *SHL(fs_reg dst, fs_reg src0, fs_reg src1);
-   fs_inst *SHR(fs_reg dst, fs_reg src0, fs_reg src1);
-   fs_inst *ASR(fs_reg dst, fs_reg src0, fs_reg src1);
-   fs_inst *AND(fs_reg dst, fs_reg src0, fs_reg src1);
-   fs_inst *OR(fs_reg dst, fs_reg src0, fs_reg src1);
-   fs_inst *XOR(fs_reg dst, fs_reg src0, fs_reg src1);
-   fs_inst *IF(uint32_t predicate);
-   fs_inst *IF(fs_reg src0, fs_reg src1, uint32_t condition);
    fs_inst *CMP(fs_reg dst, fs_reg src0, fs_reg src1,
                 uint32_t condition);
-   fs_inst *LRP(fs_reg dst, fs_reg a, fs_reg y, fs_reg x);
-   fs_inst *DEP_RESOLVE_MOV(int grf);
-   fs_inst *BFREV(fs_reg dst, fs_reg value);
-   fs_inst *BFE(fs_reg dst, fs_reg bits, fs_reg offset, fs_reg value);
-   fs_inst *BFI1(fs_reg dst, fs_reg bits, fs_reg offset);
-   fs_inst *BFI2(fs_reg dst, fs_reg bfi1_dst, fs_reg insert, fs_reg base);
-   fs_inst *FBH(fs_reg dst, fs_reg value);
-   fs_inst *FBL(fs_reg dst, fs_reg value);
-   fs_inst *CBIT(fs_reg dst, fs_reg value);
-   fs_inst *MAD(fs_reg dst, fs_reg c, fs_reg b, fs_reg a);
-   fs_inst *ADDC(fs_reg dst, fs_reg src0, fs_reg src1);
-   fs_inst *SUBB(fs_reg dst, fs_reg src0, fs_reg src1);
-   fs_inst *SEL(fs_reg dst, fs_reg src0, fs_reg src1);
 
    int type_size(const struct glsl_type *type);
    fs_inst *get_instruction_generating_reg(fs_inst *start,
diff --git a/src/mesa/drivers/dri/i965/brw_fs_emitter.cpp b/src/mesa/drivers/dri/i965/brw_fs_emitter.cpp
index 4b143f1..6f1e2dd 100644
--- a/src/mesa/drivers/dri/i965/brw_fs_emitter.cpp
+++ b/src/mesa/drivers/dri/i965/brw_fs_emitter.cpp
@@ -29,6 +29,94 @@
  */
 #include "brw_fs.h"
 
+#define ALU1(op)                                                   \
+   fs_inst *                                                       \
+   fs_emitter::op(fs_reg dst, fs_reg src0)                         \
+   {                                                               \
+      return new(mem_ctx) fs_inst(BRW_OPCODE_##op, dst, src0);     \
+   }
+
+#define ALU2(op)                                                     \
+   fs_inst *                                                         \
+   fs_emitter::op(fs_reg dst, fs_reg src0, fs_reg src1)              \
+   {                                                                 \
+      return new(mem_ctx) fs_inst(BRW_OPCODE_##op, dst, src0, src1); \
+   }
+
+#define ALU3(op)                                                           \
+   fs_inst *                                                               \
+   fs_emitter::op(fs_reg dst, fs_reg src0, fs_reg src1, fs_reg src2)       \
+   {                                                                       \
+      return new(mem_ctx) fs_inst(BRW_OPCODE_##op, dst, src0, src1, src2); \
+   }
+
+ALU1(NOT)
+ALU1(MOV)
+ALU1(FRC)
+ALU1(RNDD)
+ALU1(RNDE)
+ALU1(RNDZ)
+ALU2(ADD)
+ALU2(MUL)
+ALU2(MACH)
+ALU2(AND)
+ALU2(OR)
+ALU2(XOR)
+ALU2(SHL)
+ALU2(SHR)
+ALU2(ASR)
+ALU3(LRP)
+ALU1(BFREV)
+ALU3(BFE)
+ALU2(BFI1)
+ALU3(BFI2)
+ALU1(FBH)
+ALU1(FBL)
+ALU1(CBIT)
+ALU3(MAD)
+ALU2(ADDC)
+ALU2(SUBB)
+ALU2(SEL)
+
+/** Gen4 predicated IF. */
+fs_inst *
+fs_emitter::IF(uint32_t predicate)
+{
+   fs_inst *inst = new(mem_ctx) fs_inst(BRW_OPCODE_IF);
+   inst->predicate = predicate;
+   return inst;
+}
+
+/** Gen6 IF with embedded comparison. */
+fs_inst *
+fs_emitter::IF(fs_reg src0, fs_reg src1, uint32_t condition)
+{
+   assert(brw->gen == 6);
+   fs_inst *inst = new(mem_ctx) fs_inst(BRW_OPCODE_IF, reg_null_d, src0, src1);
+   inst->conditional_mod = condition;
+   return inst;
+}
+
+/**
+ * A helper for MOV generation for fixing up broken hardware SEND dependency
+ * handling.
+ */
+fs_inst *
+fs_emitter::DEP_RESOLVE_MOV(int grf)
+{
+   fs_inst *inst = MOV(brw_null_reg(), fs_reg(GRF, grf, BRW_REGISTER_TYPE_F));
+
+   inst->ir = NULL;
+   inst->annotation = "send dependency resolve";
+
+   /* The caller always wants uncompressed to emit the minimal extra
+    * dependencies, and to avoid having to deal with aligning its regs to 2.
+    */
+   inst->force_uncompressed = true;
+
+   return inst;
+}
+
 fs_inst *
 fs_emitter::emit(fs_inst inst)
 {
-- 
1.8.3.1



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