[Mesa-dev] [PATCH] i965: Fix sampler state pointer adjustment for nonconst samplers

[Chris Forbes]

I haven't bisected, but this will have got broken when we changed the
execsize guessing. Previously we would have picked a larger execsize
here, but now it is and(1).

This is the d/u indexing case, so sampler_index is a vec8/vec16 grf.
Most of the other cases are immediates, or individual vec1s already
extracted from the header reg etc.

On Wed, Nov 5, 2014 at 7:00 AM, Kenneth Graunke <kenneth at whitecape.org> wrote:
> On Wednesday, November 05, 2014 06:41:13 AM Chris Forbes wrote:
>> This started hitting an assertion recently. Only affects Haswell
>> (Ivybridge doesn't support this meddling with the sampler state pointer,
>> and ARB_gpu_shader5 is not enabled yet on Broadwell)
>>
>> 14 Piglits crash->pass.
>>
>> Signed-off-by: Chris Forbes <chrisf at ijw.co.nz>
>> ---
>>  src/mesa/drivers/dri/i965/brw_eu_emit.c | 2 +-
>>  1 file changed, 1 insertion(+), 1 deletion(-)
>>
>> diff --git a/src/mesa/drivers/dri/i965/brw_eu_emit.c
> b/src/mesa/drivers/dri/i965/brw_eu_emit.c
>> index bb6334b..bb12a26 100644
>> --- a/src/mesa/drivers/dri/i965/brw_eu_emit.c
>> +++ b/src/mesa/drivers/dri/i965/brw_eu_emit.c
>> @@ -2409,7 +2409,7 @@ void brw_adjust_sampler_state_pointer(struct
> brw_compile *p,
>>
>>        struct brw_reg temp = vec1(retype(scratch, BRW_REGISTER_TYPE_UD));
>>
>> -      brw_AND(p, temp, sampler_index, brw_imm_ud(0x0f0));
>> +      brw_AND(p, temp, get_element_ud(sampler_index, 0),
> brw_imm_ud(0x0f0));
>>        brw_SHL(p, temp, temp, brw_imm_ud(4));
>>        brw_ADD(p,
>>                get_element_ud(header, 3),
>>
>
> Seems like a reasonable thing to do, though I'd be curious to know why it
> broke...
>
> Notably, most of the other header accesses already explicitly do a
> get_element_ud.
>
> Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>