[Mesa-dev] [PATCH 2/2] i965/gen: Don't conflate base miplevel in sampler state

Ben Widawsky benjamin.widawsky at intel.com
Thu Aug 27 11:50:52 PDT 2015


Gen9 changes the meaning of this to coarse LOD quality mode. Although that's a
desirable thing to be setting, it doesn't match the gen8 behavior and this was
unintentional.

This doesn't fix, or regress anything on SKL (AFAICT).

Signed-off-by: Ben Widawsky <ben at bwidawsk.net>
---
 src/mesa/drivers/dri/i965/brw_sampler_state.c | 4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

diff --git a/src/mesa/drivers/dri/i965/brw_sampler_state.c b/src/mesa/drivers/dri/i965/brw_sampler_state.c
index 2021bb3..b1e339b 100644
--- a/src/mesa/drivers/dri/i965/brw_sampler_state.c
+++ b/src/mesa/drivers/dri/i965/brw_sampler_state.c
@@ -94,11 +94,13 @@ brw_emit_sampler_state(struct brw_context *brw,
                        uint32_t border_color_offset)
 {
    ss[0] = BRW_SAMPLER_LOD_PRECLAMP_ENABLE |
-           SET_FIELD(base_level, BRW_SAMPLER_BASE_MIPLEVEL) |
            SET_FIELD(mip_filter, BRW_SAMPLER_MIP_FILTER) |
            SET_FIELD(mag_filter, BRW_SAMPLER_MAG_FILTER) |
            SET_FIELD(min_filter, BRW_SAMPLER_MIN_FILTER);
 
+   if (brw->gen < 9)
+      SET_FIELD(base_level, BRW_SAMPLER_BASE_MIPLEVEL);
+
    ss[2] = border_color_offset;
    if (brw->gen < 6) {
       ss[2] += brw->batch.bo->offset64; /* reloc */
-- 
2.5.0



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