[Mesa-dev] [PATCH] i965: Add device limits for tess threads & URB entries
Kenneth Graunke
kenneth at whitecape.org
Mon Feb 9 23:51:32 PST 2015
From: Chris Forbes <chrisf at ijw.co.nz>
This should cover all platforms prior to Skylake.
Signed-off-by: Chris Forbes <chrisf at ijw.co.nz>
Signed-off-by: Kenneth Graunke <kenneth at whitecape.org>
---
src/mesa/drivers/dri/i965/brw_context.c | 4 ++++
src/mesa/drivers/dri/i965/brw_context.h | 4 ++++
src/mesa/drivers/dri/i965/brw_device_info.c | 36 +++++++++++++++++++++++++++++
src/mesa/drivers/dri/i965/brw_device_info.h | 4 ++++
4 files changed, 48 insertions(+)
Chris - I decided to just fill in the correct values for all the platforms
and send this out. We may as well merge it now; no reason not to.
diff --git a/src/mesa/drivers/dri/i965/brw_context.c b/src/mesa/drivers/dri/i965/brw_context.c
index e20da0b..50b1387 100644
--- a/src/mesa/drivers/dri/i965/brw_context.c
+++ b/src/mesa/drivers/dri/i965/brw_context.c
@@ -804,25 +804,29 @@ brwCreateContext(gl_api api,
}
}
brw_init_state(brw);
intelInitExtensions(ctx);
brw_init_surface_formats(brw);
brw->max_vs_threads = devinfo->max_vs_threads;
+ brw->max_hs_threads = devinfo->max_hs_threads;
+ brw->max_ds_threads = devinfo->max_ds_threads;
brw->max_gs_threads = devinfo->max_gs_threads;
brw->max_wm_threads = devinfo->max_wm_threads;
brw->urb.size = devinfo->urb.size;
brw->urb.min_vs_entries = devinfo->urb.min_vs_entries;
brw->urb.max_vs_entries = devinfo->urb.max_vs_entries;
+ brw->urb.max_hs_entries = devinfo->urb.max_hs_entries;
+ brw->urb.max_ds_entries = devinfo->urb.max_ds_entries;
brw->urb.max_gs_entries = devinfo->urb.max_gs_entries;
/* Estimate the size of the mappable aperture into the GTT. There's an
* ioctl to get the whole GTT size, but not one to get the mappable subset.
* It turns out it's basically always 256MB, though some ancient hardware
* was smaller.
*/
uint32_t gtt_size = 256 * 1024 * 1024;
/* We don't want to map two objects such that a memcpy between them would
diff --git a/src/mesa/drivers/dri/i965/brw_context.h b/src/mesa/drivers/dri/i965/brw_context.h
index d315793..ac19342 100644
--- a/src/mesa/drivers/dri/i965/brw_context.h
+++ b/src/mesa/drivers/dri/i965/brw_context.h
@@ -1178,35 +1178,39 @@ struct brw_context
* Number of samples in ctx->DrawBuffer, updated by BRW_NEW_NUM_SAMPLES so
* that we don't have to reemit that state every time we change FBOs.
*/
int num_samples;
/**
* Platform specific constants containing the maximum number of threads
* for each pipeline stage.
*/
int max_vs_threads;
+ int max_hs_threads;
+ int max_ds_threads;
int max_gs_threads;
int max_wm_threads;
/* BRW_NEW_URB_ALLOCATIONS:
*/
struct {
GLuint vsize; /* vertex size plus header in urb registers */
GLuint gsize; /* GS output size in urb registers */
GLuint csize; /* constant buffer size in urb registers */
GLuint sfsize; /* setup data size in urb registers */
bool constrained;
GLuint min_vs_entries; /* Minimum number of VS entries */
GLuint max_vs_entries; /* Maximum number of VS entries */
+ GLuint max_hs_entries; /* Maximum number of HS entries */
+ GLuint max_ds_entries; /* Maximum number of DS entries */
GLuint max_gs_entries; /* Maximum number of GS entries */
GLuint nr_vs_entries;
GLuint nr_gs_entries;
GLuint nr_clip_entries;
GLuint nr_sf_entries;
GLuint nr_cs_entries;
GLuint vs_start;
GLuint gs_start;
diff --git a/src/mesa/drivers/dri/i965/brw_device_info.c b/src/mesa/drivers/dri/i965/brw_device_info.c
index 3c3c564..ec4e22e 100644
--- a/src/mesa/drivers/dri/i965/brw_device_info.c
+++ b/src/mesa/drivers/dri/i965/brw_device_info.c
@@ -106,151 +106,187 @@ static const struct brw_device_info brw_device_info_snb_gt2 = {
.has_hiz_and_separate_stencil = true, \
.must_use_separate_stencil = true, \
.has_llc = true, \
.has_pln = true, \
.has_surface_tile_offset = true
static const struct brw_device_info brw_device_info_ivb_gt1 = {
GEN7_FEATURES, .is_ivybridge = true, .gt = 1,
.needs_unlit_centroid_workaround = true,
.max_vs_threads = 36,
+ .max_hs_threads = 36,
+ .max_ds_threads = 36,
.max_gs_threads = 36,
.max_wm_threads = 48,
.urb = {
.size = 128,
.min_vs_entries = 32,
.max_vs_entries = 512,
+ .max_hs_entries = 32,
+ .max_ds_entries = 288,
.max_gs_entries = 192,
},
};
static const struct brw_device_info brw_device_info_ivb_gt2 = {
GEN7_FEATURES, .is_ivybridge = true, .gt = 2,
.needs_unlit_centroid_workaround = true,
.max_vs_threads = 128,
+ .max_hs_threads = 128,
+ .max_ds_threads = 128,
.max_gs_threads = 128,
.max_wm_threads = 172,
.urb = {
.size = 256,
.min_vs_entries = 32,
.max_vs_entries = 704,
+ .max_hs_entries = 64,
+ .max_ds_entries = 448,
.max_gs_entries = 320,
},
};
static const struct brw_device_info brw_device_info_byt = {
GEN7_FEATURES, .is_baytrail = true, .gt = 1,
.needs_unlit_centroid_workaround = true,
.has_llc = false,
.max_vs_threads = 36,
+ .max_hs_threads = 36,
+ .max_ds_threads = 36,
.max_gs_threads = 36,
.max_wm_threads = 48,
.urb = {
.size = 128,
.min_vs_entries = 32,
.max_vs_entries = 512,
+ .max_hs_entries = 32,
+ .max_ds_entries = 288,
.max_gs_entries = 192,
},
};
static const struct brw_device_info brw_device_info_hsw_gt1 = {
GEN7_FEATURES, .is_haswell = true, .gt = 1,
.max_vs_threads = 70,
+ .max_hs_threads = 70,
+ .max_ds_threads = 70,
.max_gs_threads = 70,
.max_wm_threads = 102,
.urb = {
.size = 128,
.min_vs_entries = 32,
.max_vs_entries = 640,
+ .max_hs_entries = 64,
+ .max_ds_entries = 384,
.max_gs_entries = 256,
},
};
static const struct brw_device_info brw_device_info_hsw_gt2 = {
GEN7_FEATURES, .is_haswell = true, .gt = 2,
.max_vs_threads = 280,
+ .max_hs_threads = 256,
+ .max_ds_threads = 280,
.max_gs_threads = 256,
.max_wm_threads = 204,
.urb = {
.size = 256,
.min_vs_entries = 64,
.max_vs_entries = 1664,
+ .max_hs_entries = 128,
+ .max_ds_entries = 960,
.max_gs_entries = 640,
},
};
static const struct brw_device_info brw_device_info_hsw_gt3 = {
GEN7_FEATURES, .is_haswell = true, .gt = 3,
.max_vs_threads = 280,
+ .max_hs_threads = 256,
+ .max_ds_threads = 280,
.max_gs_threads = 256,
.max_wm_threads = 408,
.urb = {
.size = 512,
.min_vs_entries = 64,
.max_vs_entries = 1664,
+ .max_hs_entries = 128,
+ .max_ds_entries = 960,
.max_gs_entries = 640,
},
};
#define GEN8_FEATURES \
.gen = 8, \
.has_hiz_and_separate_stencil = true, \
.must_use_separate_stencil = true, \
.has_llc = true, \
.has_pln = true, \
.max_vs_threads = 504, \
+ .max_hs_threads = 504, \
+ .max_ds_threads = 504, \
.max_gs_threads = 504, \
.max_wm_threads = 384 \
static const struct brw_device_info brw_device_info_bdw_gt1 = {
GEN8_FEATURES, .gt = 1,
.urb = {
.size = 192,
.min_vs_entries = 64,
.max_vs_entries = 2560,
+ .max_hs_entries = 504,
+ .max_ds_entries = 1536,
.max_gs_entries = 960,
}
};
static const struct brw_device_info brw_device_info_bdw_gt2 = {
GEN8_FEATURES, .gt = 2,
.urb = {
.size = 384,
.min_vs_entries = 64,
.max_vs_entries = 2560,
+ .max_hs_entries = 504,
+ .max_ds_entries = 1536,
.max_gs_entries = 960,
}
};
static const struct brw_device_info brw_device_info_bdw_gt3 = {
GEN8_FEATURES, .gt = 3,
.urb = {
.size = 384,
.min_vs_entries = 64,
.max_vs_entries = 2560,
+ .max_hs_entries = 504,
+ .max_ds_entries = 1536,
.max_gs_entries = 960,
}
};
/* Thread counts and URB limits are placeholders, and may not be accurate.
* These were copied from Haswell GT1, above.
*/
static const struct brw_device_info brw_device_info_chv = {
GEN8_FEATURES, .is_cherryview = 1, .gt = 1,
.has_llc = false,
.max_vs_threads = 80,
+ .max_hs_threads = 80,
+ .max_ds_threads = 80,
.max_gs_threads = 80,
.max_wm_threads = 128,
.urb = {
.size = 128,
.min_vs_entries = 34,
.max_vs_entries = 640,
+ .max_hs_entries = 80,
+ .max_ds_entries = 384,
.max_gs_entries = 256,
}
};
/* Thread counts and URB limits are placeholders, and may not be accurate. */
#define GEN9_FEATURES \
.gen = 9, \
.has_hiz_and_separate_stencil = true, \
.must_use_separate_stencil = true, \
.has_llc = true, \
diff --git a/src/mesa/drivers/dri/i965/brw_device_info.h b/src/mesa/drivers/dri/i965/brw_device_info.h
index e506beb..7c9f5d0 100644
--- a/src/mesa/drivers/dri/i965/brw_device_info.h
+++ b/src/mesa/drivers/dri/i965/brw_device_info.h
@@ -59,23 +59,27 @@ struct brw_device_info
* fragment shader instructions.
*/
bool needs_unlit_centroid_workaround;
/** @} */
/**
* GPU Limits:
* @{
*/
unsigned max_vs_threads;
+ unsigned max_hs_threads;
+ unsigned max_ds_threads;
unsigned max_gs_threads;
unsigned max_wm_threads;
struct {
unsigned size;
unsigned min_vs_entries;
unsigned max_vs_entries;
+ unsigned max_hs_entries;
+ unsigned max_ds_entries;
unsigned max_gs_entries;
} urb;
/** @} */
};
const struct brw_device_info *brw_get_device_info(int devid);
--
2.2.2
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