[Mesa-dev] [RFC PATCH 05/40] i965/gen7.5: Enable hardware-generated binding tables on render path.
Kenneth Graunke
kenneth at whitecape.org
Sun Jan 4 19:36:51 PST 2015
On Sunday, January 04, 2015 04:04:19 PM Abdiel Janulgue wrote:
> This patch implements the binding table enable command which is also
> used to allocate a binding table pool where where hardware-generated
> binding table entries are flushed into.
>
> Each binding table offset in the binding table pool is unique per
> each shader stage that are enabled within a batch.
>
> In addition, this change inserts the required brw_tracked_state objects
> to enable hw-generated binding tables in normal render path.
>
> Signed-off-by: Abdiel Janulgue <abdiel.janulgue at linux.intel.com>
> ---
> src/mesa/drivers/dri/i965/brw_binding_tables.c | 67 ++++++++++++++++++++++++++
> src/mesa/drivers/dri/i965/brw_context.c | 2 +
> src/mesa/drivers/dri/i965/brw_context.h | 5 ++
> src/mesa/drivers/dri/i965/brw_defines.h | 3 ++
> src/mesa/drivers/dri/i965/brw_state.h | 12 +++++
> src/mesa/drivers/dri/i965/brw_state_upload.c | 2 +
> 6 files changed, 91 insertions(+)
>
> diff --git a/src/mesa/drivers/dri/i965/brw_binding_tables.c b/src/mesa/drivers/dri/i965/brw_binding_tables.c
> index ea82e71..3807301 100644
> --- a/src/mesa/drivers/dri/i965/brw_binding_tables.c
> +++ b/src/mesa/drivers/dri/i965/brw_binding_tables.c
> @@ -44,6 +44,7 @@
> #include "brw_state.h"
> #include "intel_batchbuffer.h"
>
> +static const int bt_size = 256 * sizeof(uint16_t);
Is this just an arbitrarily chosen size?
> /**
> * Upload a shader stage's binding table as indirect state.
> *
> @@ -161,6 +162,72 @@ const struct brw_tracked_state brw_gs_binding_table = {
> .emit = brw_gs_upload_binding_table,
> };
>
> +/**
> + * Hardware-generated binding tables for the resource streamer
> + */
> +void
> +gen7_disable_hw_binding_tables(struct brw_context *brw)
> +{
> + BEGIN_BATCH(3);
> + OUT_BATCH(_3DSTATE_BINDING_TABLE_POOL_ALLOC << 16 | (3 - 2));
> + OUT_BATCH(3 << 5); /* only in HSW */
#defines for magic values, please.
> + OUT_BATCH(0);
> + ADVANCE_BATCH();
> +
> + /* Pipe control workaround */
> + BEGIN_BATCH(4);
> + OUT_BATCH(_3DSTATE_PIPE_CONTROL | (4 - 2));
> + OUT_BATCH(PIPE_CONTROL_STATE_CACHE_INVALIDATE);
> + OUT_BATCH(0); /* address */
> + OUT_BATCH(0); /* write data */
> + ADVANCE_BATCH();
> +}
> +
> +void
> +gen7_enable_hw_binding_tables(struct brw_context *brw)
> +{
> + if (!brw->has_resource_streamer) {
> + gen7_disable_hw_binding_tables(brw);
> + return;
> + }
> +
> + if (!brw->hw_bt_pool.bo) {
> + brw->hw_bt_pool.bo = drm_intel_bo_alloc(brw->bufmgr, "hw_bt",
> + 131072, 4096);
Perhaps use bt_size here, not a hardcoded 128kB?
> + brw->hw_bt_pool.next_offset = bt_size;
> + }
> +
> + BEGIN_BATCH(3);
> + OUT_BATCH(_3DSTATE_BINDING_TABLE_POOL_ALLOC << 16 | (3 - 2));
> + OUT_RELOC(brw->hw_bt_pool.bo, I915_GEM_DOMAIN_SAMPLER, 0,
> + HSW_BINDING_TABLE_ALLOC_OFFSET | GEN7_MOCS_L3 << 7);
> + OUT_RELOC(brw->hw_bt_pool.bo, I915_GEM_DOMAIN_SAMPLER, 0,
> + brw->hw_bt_pool.bo->size);
> + ADVANCE_BATCH();
> +
> + /* Pipe control workaround */
> + BEGIN_BATCH(4);
> + OUT_BATCH(_3DSTATE_PIPE_CONTROL | (4 - 2));
> + OUT_BATCH(PIPE_CONTROL_STATE_CACHE_INVALIDATE);
> + OUT_BATCH(0); /* address */
> + OUT_BATCH(0); /* write data */
> + ADVANCE_BATCH();
brw_emit_pipe_control_flush(brw, PIPE_CONTROL_STATE_CACHE_INVALIDATE);
> +}
> +
> +void
> +gen7_reset_rs_pool_offsets(struct brw_context *brw)
> +{
> + brw->hw_bt_pool.next_offset = bt_size;
> +}
> +
> +const struct brw_tracked_state gen7_hw_binding_tables = {
> + .dirty = {
> + .mesa = 0,
> + .brw = BRW_NEW_BATCH,
> + },
> + .emit = gen7_enable_hw_binding_tables
> +};
> +
> /** @} */
>
> /**
> diff --git a/src/mesa/drivers/dri/i965/brw_context.c b/src/mesa/drivers/dri/i965/brw_context.c
> index 59f190b..b962103 100644
> --- a/src/mesa/drivers/dri/i965/brw_context.c
> +++ b/src/mesa/drivers/dri/i965/brw_context.c
> @@ -852,6 +852,8 @@ brwCreateContext(gl_api api,
> if ((flags & __DRI_CTX_FLAG_ROBUST_BUFFER_ACCESS) != 0)
> ctx->Const.ContextFlags |= GL_CONTEXT_FLAG_ROBUST_ACCESS_BIT_ARB;
>
> + brw->hw_bt_pool.bo = 0;
You don't need this - brw_context is rzalloc'd, so fields are already zeroed.
> +
> if (INTEL_DEBUG & DEBUG_SHADER_TIME)
> brw_init_shader_time(brw);
>
> diff --git a/src/mesa/drivers/dri/i965/brw_context.h b/src/mesa/drivers/dri/i965/brw_context.h
> index dd8e730..17fea5b 100644
> --- a/src/mesa/drivers/dri/i965/brw_context.h
> +++ b/src/mesa/drivers/dri/i965/brw_context.h
> @@ -1334,6 +1334,11 @@ struct brw_context
> uint32_t fast_clear_op;
> } wm;
>
> + /* RS hardware binding table */
> + struct {
> + drm_intel_bo *bo;
> + uint32_t next_offset;
> + } hw_bt_pool;
>
> struct {
> uint32_t state_offset;
> diff --git a/src/mesa/drivers/dri/i965/brw_defines.h b/src/mesa/drivers/dri/i965/brw_defines.h
> index 28e398d..ba62811 100644
> --- a/src/mesa/drivers/dri/i965/brw_defines.h
> +++ b/src/mesa/drivers/dri/i965/brw_defines.h
> @@ -1572,6 +1572,9 @@ enum brw_message_target {
> #define _3DSTATE_BINDING_TABLE_POINTERS_GS 0x7829 /* GEN7+ */
> #define _3DSTATE_BINDING_TABLE_POINTERS_PS 0x782A /* GEN7+ */
>
> +#define _3DSTATE_BINDING_TABLE_POOL_ALLOC 0x7919 /* GEN7.5+ */
> +# define HSW_BINDING_TABLE_ALLOC_OFFSET 0x860 /* GEN7.5+ */
> +
> #define _3DSTATE_SAMPLER_STATE_POINTERS 0x7802 /* GEN6+ */
> # define PS_SAMPLER_STATE_CHANGE (1 << 12)
> # define GS_SAMPLER_STATE_CHANGE (1 << 9)
> diff --git a/src/mesa/drivers/dri/i965/brw_state.h b/src/mesa/drivers/dri/i965/brw_state.h
> index 399347c..bbbf4a4 100644
> --- a/src/mesa/drivers/dri/i965/brw_state.h
> +++ b/src/mesa/drivers/dri/i965/brw_state.h
> @@ -130,6 +130,7 @@ extern const struct brw_tracked_state gen7_sol_state;
> extern const struct brw_tracked_state gen7_urb;
> extern const struct brw_tracked_state gen7_vs_state;
> extern const struct brw_tracked_state gen7_wm_state;
> +extern const struct brw_tracked_state gen7_hw_binding_tables;
> extern const struct brw_tracked_state haswell_cut_index;
> extern const struct brw_tracked_state gen8_blend_state;
> extern const struct brw_tracked_state gen8_disable_stages;
> @@ -289,6 +290,17 @@ gen7_upload_constant_state(struct brw_context *brw,
> const struct brw_stage_state *stage_state,
> bool active, unsigned opcode);
>
> +/* gen8_vs_state.c */
> +void
> +gen8_upload_constant_state(struct brw_context *brw,
> + const struct brw_stage_state *stage_state,
> + bool active, unsigned opcode);
> +/* gen7_misc_state.c */
> +void gen7_rs_control(struct brw_context *brw, int enable);
> +void gen7_enable_hw_binding_tables(struct brw_context *brw);
> +void gen7_disable_hw_binding_tables(struct brw_context *brw);
> +void gen7_reset_rs_pool_offsets(struct brw_context *brw);
> +
> #ifdef __cplusplus
> }
> #endif
> diff --git a/src/mesa/drivers/dri/i965/brw_state_upload.c b/src/mesa/drivers/dri/i965/brw_state_upload.c
> index a579781..612638e 100644
> --- a/src/mesa/drivers/dri/i965/brw_state_upload.c
> +++ b/src/mesa/drivers/dri/i965/brw_state_upload.c
> @@ -198,6 +198,8 @@ static const struct brw_tracked_state *gen7_atoms[] =
> &gen6_color_calc_state, /* must do before cc unit */
> &gen6_depth_stencil_state, /* must do before cc unit */
>
> + &gen7_hw_binding_tables, /* Enable hw-generated binding tables for Haswell */
> +
> &gen6_vs_push_constants, /* Before vs_state */
> &gen6_gs_push_constants, /* Before gs_state */
> &gen6_wm_push_constants, /* Before wm_surfaces and constant_buffer */
>
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