[Mesa-dev] [PATCH 4/4] i965/nir: Enable SIMD16 support in the NIR FS backend.

[Jason Ekstrand]

Two stupid questions:

1) Did you gun piglit with INTEL_USE_NIR and did everything check out OK?

2) Did you grep fs_nir.cpp for virtual_grf_alloc and reg_offset to make
sure you didn't miss anything?

If the answer to both of the above is yes, this series is

Reviewed-by: Jason Ekstrand <jason.ekstrand at intel.com>
On Jan 16, 2015 4:19 PM, "Kenneth Graunke" <kenneth at whitecape.org> wrote:

> With the previous commits in place, it just works.
>
> Signed-off-by: Kenneth Graunke <kenneth at whitecape.org>
> ---
>  src/mesa/drivers/dri/i965/brw_fs.cpp | 3 +--
>  1 file changed, 1 insertion(+), 2 deletions(-)
>
> diff --git a/src/mesa/drivers/dri/i965/brw_fs.cpp
> b/src/mesa/drivers/dri/i965/brw_fs.cpp
> index 6490788..786e4e0 100644
> --- a/src/mesa/drivers/dri/i965/brw_fs.cpp
> +++ b/src/mesa/drivers/dri/i965/brw_fs.cpp
> @@ -3753,8 +3753,7 @@ fs_visitor::run_fs()
>         * functions called "main").
>         */
>        if (shader) {
> -         if (getenv("INTEL_USE_NIR") != NULL && !brw->use_rep_send) {
> -            no16("Cannot do 16-wide in NIR yet");
> +         if (getenv("INTEL_USE_NIR") != NULL) {
>              emit_nir_code();
>           } else {
>              foreach_in_list(ir_instruction, ir, shader->base.ir) {
> --
> 2.2.2
>
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