[Mesa-dev] [PATCH 1/3] i965/gen4-5: Set ENDIF dst and src0 fields to the null register.

[Kenneth Graunke]

On Monday, July 06, 2015 09:03:35 PM Francisco Jerez wrote:
> The hardware docs don't mention explicitly what these fields should
> be, but I've verified experimentally on ILK that using a GRF as
> destination causes the register to be corrupted when the execution
> size of an ENDIF instruction is higher than 8 -- and because the
> destination we were using was g0, eventually a hang.
> 
> Fixes some 150 piglit tests on Gen4-5 when forced to run shaders with
> if conditionals 16-wide, e.g. shaders/glsl-fs-sampler-numbering-3.
> ---
>  src/mesa/drivers/dri/i965/brw_eu_emit.c | 4 ++--
>  1 file changed, 2 insertions(+), 2 deletions(-)
> 
> diff --git a/src/mesa/drivers/dri/i965/brw_eu_emit.c b/src/mesa/drivers/dri/i965/brw_eu_emit.c
> index 0f53604..4d39762 100644
> --- a/src/mesa/drivers/dri/i965/brw_eu_emit.c
> +++ b/src/mesa/drivers/dri/i965/brw_eu_emit.c
> @@ -1584,8 +1584,8 @@ brw_ENDIF(struct brw_codegen *p)
>     }
>  
>     if (devinfo->gen < 6) {
> -      brw_set_dest(p, insn, retype(brw_vec4_grf(0,0), BRW_REGISTER_TYPE_UD));
> -      brw_set_src0(p, insn, retype(brw_vec4_grf(0,0), BRW_REGISTER_TYPE_UD));
> +      brw_set_dest(p, insn, retype(brw_null_reg(), BRW_REGISTER_TYPE_D));
> +      brw_set_src0(p, insn, retype(brw_null_reg(), BRW_REGISTER_TYPE_D));
>        brw_set_src1(p, insn, brw_imm_d(0x0));
>     } else if (devinfo->gen == 6) {
>        brw_set_dest(p, insn, brw_imm_w(0));
> 

Hah!  I always thought there were just some bugs in this area, but I'm
surprised to see that they were so small.  Great work tracking them
down!

We were doing a bunch of other bogus stuff back in the day, but some of
that got fixed during the Gen4-7 and Gen8+ code generator merging.

Nice work :) Series is:
Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>
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