[Mesa-dev] [PATCH 06/23] i965/gen9: Set tiled resource mode for the miptree

[Anuj Phogat]

Signed-off-by: Anuj Phogat <anuj.phogat at gmail.com>
---
 src/mesa/drivers/dri/i965/brw_tex_layout.c    | 2 ++
 src/mesa/drivers/dri/i965/intel_mipmap_tree.h | 6 ++++++
 2 files changed, 8 insertions(+)

diff --git a/src/mesa/drivers/dri/i965/brw_tex_layout.c b/src/mesa/drivers/dri/i965/brw_tex_layout.c
index 499c2dc..eab3884 100644
--- a/src/mesa/drivers/dri/i965/brw_tex_layout.c
+++ b/src/mesa/drivers/dri/i965/brw_tex_layout.c
@@ -539,6 +539,8 @@ brw_miptree_layout(struct brw_context *brw,
 {
    bool gen6_hiz_or_stencil = false;
 
+   mt->tr_mode = INTEL_MIPTREE_TRMODE_NONE;
+
    if (brw->gen == 6 && mt->array_layout == ALL_SLICES_AT_EACH_LOD) {
       const GLenum base_format = _mesa_get_format_base_format(mt->format);
       gen6_hiz_or_stencil = _mesa_is_depth_or_stencil_format(base_format);
diff --git a/src/mesa/drivers/dri/i965/intel_mipmap_tree.h b/src/mesa/drivers/dri/i965/intel_mipmap_tree.h
index 55f012a..278a44e 100644
--- a/src/mesa/drivers/dri/i965/intel_mipmap_tree.h
+++ b/src/mesa/drivers/dri/i965/intel_mipmap_tree.h
@@ -315,6 +315,7 @@ struct intel_mipmap_tree
    uint32_t pitch; /**< pitch in bytes. */
 
    uint32_t tiling; /**< One of the I915_TILING_* flags */
+   uint32_t tr_mode; /**< One of the INTEL_MIPTREE_TRMODE_* flags */
 
    /* Effectively the key:
     */
@@ -480,6 +481,11 @@ enum intel_miptree_tiling_mode {
    INTEL_MIPTREE_TILING_NONE,
 };
 
+/* Tile resource modes */
+#define   INTEL_MIPTREE_TRMODE_NONE    0
+#define   INTEL_MIPTREE_TRMODE_YF      1
+#define   INTEL_MIPTREE_TRMODE_YS      2
+
 bool
 intel_is_non_msrt_mcs_buffer_supported(struct brw_context *brw,
                                        struct intel_mipmap_tree *mt);
-- 
2.3.4