[Mesa-dev] [PATCH 6/7] i965: Move opcode_desc tables into brw_eu.c.
Francisco Jerez
currojerez at riseup.net
Thu Apr 28 07:19:17 UTC 2016
The opcode_desc tables are useful for several purposes other than
disassembling the program: Finding out whether an instruction is
three-source in the optimizer and instruction compaction code,
printing out instructions at the IR level and validating assembled
programs -- It seems like brw_eu.c next to other EU ISA auxiliary code
is a better fit than the disassembler.
---
src/mesa/drivers/dri/i965/brw_context.h | 6 --
src/mesa/drivers/dri/i965/brw_disasm.c | 147 --------------------------------
src/mesa/drivers/dri/i965/brw_eu.c | 147 ++++++++++++++++++++++++++++++++
src/mesa/drivers/dri/i965/brw_eu.h | 6 ++
4 files changed, 153 insertions(+), 153 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_context.h b/src/mesa/drivers/dri/i965/brw_context.h
index c001c6a..7468dfa 100644
--- a/src/mesa/drivers/dri/i965/brw_context.h
+++ b/src/mesa/drivers/dri/i965/brw_context.h
@@ -1794,12 +1794,6 @@ bool brw_lower_texture_gradients(struct brw_context *brw,
struct exec_list *instructions);
bool brw_do_lower_unnormalized_offset(struct exec_list *instructions);
-struct opcode_desc {
- char *name;
- int nsrc;
- int ndst;
-};
-
extern const char * const conditional_modifier[16];
extern const char *const pred_ctrl_align16[16];
diff --git a/src/mesa/drivers/dri/i965/brw_disasm.c b/src/mesa/drivers/dri/i965/brw_disasm.c
index 5c6f3e2..1778419 100644
--- a/src/mesa/drivers/dri/i965/brw_disasm.c
+++ b/src/mesa/drivers/dri/i965/brw_disasm.c
@@ -30,153 +30,6 @@
#include "brw_inst.h"
#include "brw_eu.h"
-/**
- * Special opcode_desc entry that marks the instruction as no longer existing.
- * Unless explicitly specified using this marker a hardware generation is
- * assumed to have inherited all opcodes defined and not removed by previous
- * generations.
- */
-#define REMOVED { .name = "***removed***", .nsrc = ~0, .ndst = ~0 }
-
-static const struct opcode_desc gen4_opcode_descs[128] = {
- [BRW_OPCODE_MOV] = { .name = "mov", .nsrc = 1, .ndst = 1 },
- [BRW_OPCODE_FRC] = { .name = "frc", .nsrc = 1, .ndst = 1 },
- [BRW_OPCODE_RNDU] = { .name = "rndu", .nsrc = 1, .ndst = 1 },
- [BRW_OPCODE_RNDD] = { .name = "rndd", .nsrc = 1, .ndst = 1 },
- [BRW_OPCODE_RNDE] = { .name = "rnde", .nsrc = 1, .ndst = 1 },
- [BRW_OPCODE_RNDZ] = { .name = "rndz", .nsrc = 1, .ndst = 1 },
- [BRW_OPCODE_NOT] = { .name = "not", .nsrc = 1, .ndst = 1 },
- [BRW_OPCODE_LZD] = { .name = "lzd", .nsrc = 1, .ndst = 1 },
-
- [BRW_OPCODE_MUL] = { .name = "mul", .nsrc = 2, .ndst = 1 },
- [BRW_OPCODE_MAC] = { .name = "mac", .nsrc = 2, .ndst = 1 },
- [BRW_OPCODE_MACH] = { .name = "mach", .nsrc = 2, .ndst = 1 },
- [BRW_OPCODE_LINE] = { .name = "line", .nsrc = 2, .ndst = 1 },
- [BRW_OPCODE_SAD2] = { .name = "sad2", .nsrc = 2, .ndst = 1 },
- [BRW_OPCODE_SADA2] = { .name = "sada2", .nsrc = 2, .ndst = 1 },
- [BRW_OPCODE_DP4] = { .name = "dp4", .nsrc = 2, .ndst = 1 },
- [BRW_OPCODE_DPH] = { .name = "dph", .nsrc = 2, .ndst = 1 },
- [BRW_OPCODE_DP3] = { .name = "dp3", .nsrc = 2, .ndst = 1 },
- [BRW_OPCODE_DP2] = { .name = "dp2", .nsrc = 2, .ndst = 1 },
-
- [BRW_OPCODE_AVG] = { .name = "avg", .nsrc = 2, .ndst = 1 },
- [BRW_OPCODE_ADD] = { .name = "add", .nsrc = 2, .ndst = 1 },
- [BRW_OPCODE_SEL] = { .name = "sel", .nsrc = 2, .ndst = 1 },
- [BRW_OPCODE_AND] = { .name = "and", .nsrc = 2, .ndst = 1 },
- [BRW_OPCODE_OR] = { .name = "or", .nsrc = 2, .ndst = 1 },
- [BRW_OPCODE_XOR] = { .name = "xor", .nsrc = 2, .ndst = 1 },
- [BRW_OPCODE_SHR] = { .name = "shr", .nsrc = 2, .ndst = 1 },
- [BRW_OPCODE_SHL] = { .name = "shl", .nsrc = 2, .ndst = 1 },
- [BRW_OPCODE_ASR] = { .name = "asr", .nsrc = 2, .ndst = 1 },
- [BRW_OPCODE_CMP] = { .name = "cmp", .nsrc = 2, .ndst = 1 },
- [BRW_OPCODE_CMPN] = { .name = "cmpn", .nsrc = 2, .ndst = 1 },
-
- [BRW_OPCODE_SEND] = { .name = "send", .nsrc = 1, .ndst = 1 },
- [BRW_OPCODE_SENDC] = { .name = "sendc", .nsrc = 1, .ndst = 1 },
- [BRW_OPCODE_ILLEGAL] = { .name = "illegal", .nsrc = 0, .ndst = 0 },
- [BRW_OPCODE_NOP] = { .name = "nop", .nsrc = 0, .ndst = 0 },
- [BRW_OPCODE_NENOP] = { .name = "nenop", .nsrc = 0, .ndst = 0 },
- [BRW_OPCODE_JMPI] = { .name = "jmpi", .nsrc = 0, .ndst = 0 },
- [BRW_OPCODE_IF] = { .name = "if", .nsrc = 0, .ndst = 0 },
- [BRW_OPCODE_IFF] = { .name = "iff", .nsrc = 0, .ndst = 0 },
- [BRW_OPCODE_WHILE] = { .name = "while", .nsrc = 0, .ndst = 0 },
- [BRW_OPCODE_ELSE] = { .name = "else", .nsrc = 0, .ndst = 0 },
- [BRW_OPCODE_BREAK] = { .name = "break", .nsrc = 0, .ndst = 0 },
- [BRW_OPCODE_CONTINUE] = { .name = "cont", .nsrc = 0, .ndst = 0 },
- [BRW_OPCODE_HALT] = { .name = "halt", .nsrc = 0, .ndst = 0 },
- // [BRW_OPCODE_MSAVE] = { .name = "msave", .nsrc = 1, .ndst = 1 },
- // [BRW_OPCODE_PUSH] = { .name = "push", .nsrc = 1, .ndst = 1 },
- // [BRW_OPCODE_MREST] = { .name = "mrest", .nsrc = 1, .ndst = 1 },
- // [BRW_OPCODE_POP] = { .name = "pop", .nsrc = 2, .ndst = 0 },
- [BRW_OPCODE_WAIT] = { .name = "wait", .nsrc = 1, .ndst = 0 },
- [BRW_OPCODE_DO] = { .name = "do", .nsrc = 0, .ndst = 0 },
- [BRW_OPCODE_ENDIF] = { .name = "endif", .nsrc = 0, .ndst = 0 },
-};
-
-static const struct opcode_desc g45_opcode_descs[128] = {
- [BRW_OPCODE_MOVI] = { .name = "movi", .nsrc = 2, .ndst = 1 },
- [BRW_OPCODE_PLN] = { .name = "pln", .nsrc = 2, .ndst = 1 },
-};
-
-static const struct opcode_desc gen6_opcode_descs[128] = {
- [BRW_OPCODE_MATH] = { .name = "math", .nsrc = 2, .ndst = 1 },
- [BRW_OPCODE_MAD] = { .name = "mad", .nsrc = 3, .ndst = 1 },
- [BRW_OPCODE_LRP] = { .name = "lrp", .nsrc = 3, .ndst = 1 },
- [BRW_OPCODE_IFF] = REMOVED,
- [BRW_OPCODE_DO] = REMOVED,
-};
-
-static const struct opcode_desc gen7_opcode_descs[128] = {
- [BRW_OPCODE_F32TO16] = { .name = "f32to16", .nsrc = 1, .ndst = 1 },
- [BRW_OPCODE_F16TO32] = { .name = "f16to32", .nsrc = 1, .ndst = 1 },
- [BRW_OPCODE_BFREV] = { .name = "bfrev", .nsrc = 1, .ndst = 1 },
- [BRW_OPCODE_BFE] = { .name = "bfe", .nsrc = 3, .ndst = 1 },
- [BRW_OPCODE_BFI1] = { .name = "bfi1", .nsrc = 2, .ndst = 1 },
- [BRW_OPCODE_BFI2] = { .name = "bfi2", .nsrc = 3, .ndst = 1 },
- [BRW_OPCODE_FBH] = { .name = "fbh", .nsrc = 1, .ndst = 1 },
- [BRW_OPCODE_FBL] = { .name = "fbl", .nsrc = 1, .ndst = 1 },
- [BRW_OPCODE_CBIT] = { .name = "cbit", .nsrc = 1, .ndst = 1 },
- [BRW_OPCODE_ADDC] = { .name = "addc", .nsrc = 2, .ndst = 1 },
- [BRW_OPCODE_SUBB] = { .name = "subb", .nsrc = 2, .ndst = 1 },
-};
-
-static const struct opcode_desc gen8_opcode_descs[128] = {
- [BRW_OPCODE_F32TO16] = REMOVED,
- [BRW_OPCODE_F16TO32] = REMOVED,
- [BRW_OPCODE_CSEL] = { .name = "csel", .nsrc = 3, .ndst = 1 },
-};
-
-static const struct opcode_desc gen9_opcode_descs[128] = {
- [BRW_OPCODE_SENDS] = { .name = "sends", .nsrc = 2, .ndst = 1 },
- [BRW_OPCODE_SENDSC] = { .name = "sendsc", .nsrc = 2, .ndst = 1 },
-};
-
-/**
- * Return the most recent generation-specific instruction table that
- * (re)defined the meaning of a given opcode number.
- */
-static const struct opcode_desc *
-opcode_desc_table_for(const struct brw_device_info *devinfo, enum opcode opcode)
-{
- if (devinfo->gen >= 9 && gen9_opcode_descs[opcode].name)
- return gen9_opcode_descs;
-
- else if (devinfo->gen >= 8 && gen8_opcode_descs[opcode].name)
- return gen8_opcode_descs;
-
- else if (devinfo->gen >= 7 && gen7_opcode_descs[opcode].name)
- return gen7_opcode_descs;
-
- else if (devinfo->gen >= 6 && gen6_opcode_descs[opcode].name)
- return gen6_opcode_descs;
-
- else if ((devinfo->gen >= 5 || devinfo->is_g4x) &&
- g45_opcode_descs[opcode].name)
- return g45_opcode_descs;
-
- else if (gen4_opcode_descs[opcode].name)
- return gen4_opcode_descs;
-
- else
- return NULL;
-}
-
-/* Return the matching opcode_desc for the specified opcode number and
- * hardware generation, or NULL if the opcode is not supported by the device.
- */
-const struct opcode_desc *
-brw_opcode_desc(const struct brw_device_info *devinfo, enum opcode opcode)
-{
- const struct opcode_desc *opcode_descs =
- opcode_desc_table_for(devinfo, opcode);
-
- if (opcode_descs && (opcode_descs[opcode].nsrc != ~0 &&
- opcode_descs[opcode].ndst != ~0))
- return &opcode_descs[opcode];
- else
- return NULL;
-}
-
static bool
has_jip(const struct brw_device_info *devinfo, enum opcode opcode)
{
diff --git a/src/mesa/drivers/dri/i965/brw_eu.c b/src/mesa/drivers/dri/i965/brw_eu.c
index 6961a88..88cc736 100644
--- a/src/mesa/drivers/dri/i965/brw_eu.c
+++ b/src/mesa/drivers/dri/i965/brw_eu.c
@@ -339,3 +339,150 @@ brw_disassemble(const struct brw_device_info *devinfo,
brw_disassemble_inst(out, devinfo, insn, compacted);
}
}
+
+/**
+ * Special opcode_desc entry that marks the instruction as no longer existing.
+ * Unless explicitly specified using this marker a hardware generation is
+ * assumed to have inherited all opcodes defined and not removed by previous
+ * generations.
+ */
+#define REMOVED { .name = "***removed***", .nsrc = ~0, .ndst = ~0 }
+
+static const struct opcode_desc gen4_opcode_descs[128] = {
+ [BRW_OPCODE_MOV] = { .name = "mov", .nsrc = 1, .ndst = 1 },
+ [BRW_OPCODE_FRC] = { .name = "frc", .nsrc = 1, .ndst = 1 },
+ [BRW_OPCODE_RNDU] = { .name = "rndu", .nsrc = 1, .ndst = 1 },
+ [BRW_OPCODE_RNDD] = { .name = "rndd", .nsrc = 1, .ndst = 1 },
+ [BRW_OPCODE_RNDE] = { .name = "rnde", .nsrc = 1, .ndst = 1 },
+ [BRW_OPCODE_RNDZ] = { .name = "rndz", .nsrc = 1, .ndst = 1 },
+ [BRW_OPCODE_NOT] = { .name = "not", .nsrc = 1, .ndst = 1 },
+ [BRW_OPCODE_LZD] = { .name = "lzd", .nsrc = 1, .ndst = 1 },
+
+ [BRW_OPCODE_MUL] = { .name = "mul", .nsrc = 2, .ndst = 1 },
+ [BRW_OPCODE_MAC] = { .name = "mac", .nsrc = 2, .ndst = 1 },
+ [BRW_OPCODE_MACH] = { .name = "mach", .nsrc = 2, .ndst = 1 },
+ [BRW_OPCODE_LINE] = { .name = "line", .nsrc = 2, .ndst = 1 },
+ [BRW_OPCODE_SAD2] = { .name = "sad2", .nsrc = 2, .ndst = 1 },
+ [BRW_OPCODE_SADA2] = { .name = "sada2", .nsrc = 2, .ndst = 1 },
+ [BRW_OPCODE_DP4] = { .name = "dp4", .nsrc = 2, .ndst = 1 },
+ [BRW_OPCODE_DPH] = { .name = "dph", .nsrc = 2, .ndst = 1 },
+ [BRW_OPCODE_DP3] = { .name = "dp3", .nsrc = 2, .ndst = 1 },
+ [BRW_OPCODE_DP2] = { .name = "dp2", .nsrc = 2, .ndst = 1 },
+
+ [BRW_OPCODE_AVG] = { .name = "avg", .nsrc = 2, .ndst = 1 },
+ [BRW_OPCODE_ADD] = { .name = "add", .nsrc = 2, .ndst = 1 },
+ [BRW_OPCODE_SEL] = { .name = "sel", .nsrc = 2, .ndst = 1 },
+ [BRW_OPCODE_AND] = { .name = "and", .nsrc = 2, .ndst = 1 },
+ [BRW_OPCODE_OR] = { .name = "or", .nsrc = 2, .ndst = 1 },
+ [BRW_OPCODE_XOR] = { .name = "xor", .nsrc = 2, .ndst = 1 },
+ [BRW_OPCODE_SHR] = { .name = "shr", .nsrc = 2, .ndst = 1 },
+ [BRW_OPCODE_SHL] = { .name = "shl", .nsrc = 2, .ndst = 1 },
+ [BRW_OPCODE_ASR] = { .name = "asr", .nsrc = 2, .ndst = 1 },
+ [BRW_OPCODE_CMP] = { .name = "cmp", .nsrc = 2, .ndst = 1 },
+ [BRW_OPCODE_CMPN] = { .name = "cmpn", .nsrc = 2, .ndst = 1 },
+
+ [BRW_OPCODE_SEND] = { .name = "send", .nsrc = 1, .ndst = 1 },
+ [BRW_OPCODE_SENDC] = { .name = "sendc", .nsrc = 1, .ndst = 1 },
+ [BRW_OPCODE_ILLEGAL] = { .name = "illegal", .nsrc = 0, .ndst = 0 },
+ [BRW_OPCODE_NOP] = { .name = "nop", .nsrc = 0, .ndst = 0 },
+ [BRW_OPCODE_NENOP] = { .name = "nenop", .nsrc = 0, .ndst = 0 },
+ [BRW_OPCODE_JMPI] = { .name = "jmpi", .nsrc = 0, .ndst = 0 },
+ [BRW_OPCODE_IF] = { .name = "if", .nsrc = 0, .ndst = 0 },
+ [BRW_OPCODE_IFF] = { .name = "iff", .nsrc = 0, .ndst = 0 },
+ [BRW_OPCODE_WHILE] = { .name = "while", .nsrc = 0, .ndst = 0 },
+ [BRW_OPCODE_ELSE] = { .name = "else", .nsrc = 0, .ndst = 0 },
+ [BRW_OPCODE_BREAK] = { .name = "break", .nsrc = 0, .ndst = 0 },
+ [BRW_OPCODE_CONTINUE] = { .name = "cont", .nsrc = 0, .ndst = 0 },
+ [BRW_OPCODE_HALT] = { .name = "halt", .nsrc = 0, .ndst = 0 },
+ // [BRW_OPCODE_MSAVE] = { .name = "msave", .nsrc = 1, .ndst = 1 },
+ // [BRW_OPCODE_PUSH] = { .name = "push", .nsrc = 1, .ndst = 1 },
+ // [BRW_OPCODE_MREST] = { .name = "mrest", .nsrc = 1, .ndst = 1 },
+ // [BRW_OPCODE_POP] = { .name = "pop", .nsrc = 2, .ndst = 0 },
+ [BRW_OPCODE_WAIT] = { .name = "wait", .nsrc = 1, .ndst = 0 },
+ [BRW_OPCODE_DO] = { .name = "do", .nsrc = 0, .ndst = 0 },
+ [BRW_OPCODE_ENDIF] = { .name = "endif", .nsrc = 0, .ndst = 0 },
+};
+
+static const struct opcode_desc g45_opcode_descs[128] = {
+ [BRW_OPCODE_MOVI] = { .name = "movi", .nsrc = 2, .ndst = 1 },
+ [BRW_OPCODE_PLN] = { .name = "pln", .nsrc = 2, .ndst = 1 },
+};
+
+static const struct opcode_desc gen6_opcode_descs[128] = {
+ [BRW_OPCODE_MATH] = { .name = "math", .nsrc = 2, .ndst = 1 },
+ [BRW_OPCODE_MAD] = { .name = "mad", .nsrc = 3, .ndst = 1 },
+ [BRW_OPCODE_LRP] = { .name = "lrp", .nsrc = 3, .ndst = 1 },
+ [BRW_OPCODE_IFF] = REMOVED,
+ [BRW_OPCODE_DO] = REMOVED,
+};
+
+static const struct opcode_desc gen7_opcode_descs[128] = {
+ [BRW_OPCODE_F32TO16] = { .name = "f32to16", .nsrc = 1, .ndst = 1 },
+ [BRW_OPCODE_F16TO32] = { .name = "f16to32", .nsrc = 1, .ndst = 1 },
+ [BRW_OPCODE_BFREV] = { .name = "bfrev", .nsrc = 1, .ndst = 1 },
+ [BRW_OPCODE_BFE] = { .name = "bfe", .nsrc = 3, .ndst = 1 },
+ [BRW_OPCODE_BFI1] = { .name = "bfi1", .nsrc = 2, .ndst = 1 },
+ [BRW_OPCODE_BFI2] = { .name = "bfi2", .nsrc = 3, .ndst = 1 },
+ [BRW_OPCODE_FBH] = { .name = "fbh", .nsrc = 1, .ndst = 1 },
+ [BRW_OPCODE_FBL] = { .name = "fbl", .nsrc = 1, .ndst = 1 },
+ [BRW_OPCODE_CBIT] = { .name = "cbit", .nsrc = 1, .ndst = 1 },
+ [BRW_OPCODE_ADDC] = { .name = "addc", .nsrc = 2, .ndst = 1 },
+ [BRW_OPCODE_SUBB] = { .name = "subb", .nsrc = 2, .ndst = 1 },
+};
+
+static const struct opcode_desc gen8_opcode_descs[128] = {
+ [BRW_OPCODE_F32TO16] = REMOVED,
+ [BRW_OPCODE_F16TO32] = REMOVED,
+ [BRW_OPCODE_CSEL] = { .name = "csel", .nsrc = 3, .ndst = 1 },
+};
+
+static const struct opcode_desc gen9_opcode_descs[128] = {
+ [BRW_OPCODE_SENDS] = { .name = "sends", .nsrc = 2, .ndst = 1 },
+ [BRW_OPCODE_SENDSC] = { .name = "sendsc", .nsrc = 2, .ndst = 1 },
+};
+
+/**
+ * Return the most recent generation-specific instruction table that
+ * (re)defined the meaning of a given opcode number.
+ */
+static const struct opcode_desc *
+opcode_desc_table_for(const struct brw_device_info *devinfo, enum opcode opcode)
+{
+ if (devinfo->gen >= 9 && gen9_opcode_descs[opcode].name)
+ return gen9_opcode_descs;
+
+ else if (devinfo->gen >= 8 && gen8_opcode_descs[opcode].name)
+ return gen8_opcode_descs;
+
+ else if (devinfo->gen >= 7 && gen7_opcode_descs[opcode].name)
+ return gen7_opcode_descs;
+
+ else if (devinfo->gen >= 6 && gen6_opcode_descs[opcode].name)
+ return gen6_opcode_descs;
+
+ else if ((devinfo->gen >= 5 || devinfo->is_g4x) &&
+ g45_opcode_descs[opcode].name)
+ return g45_opcode_descs;
+
+ else if (gen4_opcode_descs[opcode].name)
+ return gen4_opcode_descs;
+
+ else
+ return NULL;
+}
+
+/* Return the matching opcode_desc for the specified opcode number and
+ * hardware generation, or NULL if the opcode is not supported by the device.
+ */
+const struct opcode_desc *
+brw_opcode_desc(const struct brw_device_info *devinfo, enum opcode opcode)
+{
+ const struct opcode_desc *opcode_descs =
+ opcode_desc_table_for(devinfo, opcode);
+
+ if (opcode_descs && (opcode_descs[opcode].nsrc != ~0 &&
+ opcode_descs[opcode].ndst != ~0))
+ return &opcode_descs[opcode];
+ else
+ return NULL;
+}
diff --git a/src/mesa/drivers/dri/i965/brw_eu.h b/src/mesa/drivers/dri/i965/brw_eu.h
index 563a105..747dbc8 100644
--- a/src/mesa/drivers/dri/i965/brw_eu.h
+++ b/src/mesa/drivers/dri/i965/brw_eu.h
@@ -545,6 +545,12 @@ next_offset(const struct brw_device_info *devinfo, void *store, int offset)
return offset + 16;
}
+struct opcode_desc {
+ char *name;
+ int nsrc;
+ int ndst;
+};
+
const struct opcode_desc *
brw_opcode_desc(const struct brw_device_info *devinfo, enum opcode opcode);
--
2.7.3
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