[Mesa-dev] [PATCH 6/7] radeonsi: program multi draw and indirect draw count parameters

[Nicolai Hähnle]

From: Nicolai Hähnle <nicolai.haehnle at amd.com>

---
 src/gallium/drivers/radeonsi/si_state_draw.c | 23 ++++++++++++++++++-----
 1 file changed, 18 insertions(+), 5 deletions(-)

diff --git a/src/gallium/drivers/radeonsi/si_state_draw.c b/src/gallium/drivers/radeonsi/si_state_draw.c
index a918f85..46dd5c7 100644
--- a/src/gallium/drivers/radeonsi/si_state_draw.c
+++ b/src/gallium/drivers/radeonsi/si_state_draw.c
@@ -643,17 +643,30 @@ static void si_emit_draw_packets(struct si_context *sctx,
 			radeon_emit(cs, (sh_base_reg + SI_SGPR_START_INSTANCE * 4 - SI_SH_REG_OFFSET) >> 2);
 			radeon_emit(cs, di_src_sel);
 		} else {
+			uint64_t count_va = 0;
+
+			if (info->indirect_params) {
+				struct r600_resource *params_buf =
+					(struct r600_resource *)info->indirect_params;
+
+				radeon_add_to_buffer_list(
+					&sctx->b, &sctx->b.gfx, params_buf,
+					RADEON_USAGE_READ, RADEON_PRIO_DRAW_INDIRECT);
+
+				count_va = params_buf->gpu_address + info->indirect_params_offset;
+			}
+
 			radeon_emit(cs, PKT3(info->indexed ? PKT3_DRAW_INDEX_INDIRECT_MULTI :
 							     PKT3_DRAW_INDIRECT_MULTI,
 					     8, render_cond_bit));
 			radeon_emit(cs, info->indirect_offset);
 			radeon_emit(cs, (sh_base_reg + SI_SGPR_BASE_VERTEX * 4 - SI_SH_REG_OFFSET) >> 2);
 			radeon_emit(cs, (sh_base_reg + SI_SGPR_START_INSTANCE * 4 - SI_SH_REG_OFFSET) >> 2);
-			radeon_emit(cs, 0); /* draw_index */
-			radeon_emit(cs, 1); /* count */
-			radeon_emit(cs, 0); /* count_addr -- disabled */
-			radeon_emit(cs, 0);
-			radeon_emit(cs, 16); /* stride */
+			radeon_emit(cs, info->drawid);
+			radeon_emit(cs, info->indirect_count);
+			radeon_emit(cs, count_va);
+			radeon_emit(cs, count_va >> 32);
+			radeon_emit(cs, info->indirect_stride);
 			radeon_emit(cs, di_src_sel);
 		}
 	} else {
-- 
2.7.4