[Mesa-dev] [PATCH 27/27] [rfc] radeonsi: enable 64-bit integer support.
Dave Airlie
airlied at gmail.com
Mon Jun 20 05:07:13 UTC 2016
From: Dave Airlie <airlied at redhat.com>
This passes all my current piglit tests except the variants on:
fs-op-div-int64_t-i64vec3
I'm guessing this is probably a backend bug.
[rfc: this needs more testing - just posting to show I've done
it]
Signed-off-by: Dave Airlie <airlied at redhat.com>
---
src/gallium/drivers/radeon/radeon_llvm.h | 3 ++
.../drivers/radeon/radeon_setup_tgsi_llvm.c | 61 +++++++++++++++++++---
src/gallium/drivers/radeonsi/si_pipe.c | 1 +
3 files changed, 58 insertions(+), 7 deletions(-)
diff --git a/src/gallium/drivers/radeon/radeon_llvm.h b/src/gallium/drivers/radeon/radeon_llvm.h
index ec16def..a56a655 100644
--- a/src/gallium/drivers/radeon/radeon_llvm.h
+++ b/src/gallium/drivers/radeon/radeon_llvm.h
@@ -114,6 +114,9 @@ static inline LLVMTypeRef tgsi2llvmtype(
case TGSI_TYPE_UNSIGNED:
case TGSI_TYPE_SIGNED:
return LLVMInt32TypeInContext(ctx);
+ case TGSI_TYPE_UNSIGNED64:
+ case TGSI_TYPE_SIGNED64:
+ return LLVMInt64TypeInContext(ctx);
case TGSI_TYPE_DOUBLE:
return LLVMDoubleTypeInContext(ctx);
case TGSI_TYPE_UNTYPED:
diff --git a/src/gallium/drivers/radeon/radeon_setup_tgsi_llvm.c b/src/gallium/drivers/radeon/radeon_setup_tgsi_llvm.c
index 8084a20..7227648 100644
--- a/src/gallium/drivers/radeon/radeon_setup_tgsi_llvm.c
+++ b/src/gallium/drivers/radeon/radeon_setup_tgsi_llvm.c
@@ -884,12 +884,18 @@ static void emit_icmp(
LLVMContextRef context = bld_base->base.gallivm->context;
switch (emit_data->inst->Instruction.Opcode) {
- case TGSI_OPCODE_USEQ: pred = LLVMIntEQ; break;
- case TGSI_OPCODE_USNE: pred = LLVMIntNE; break;
- case TGSI_OPCODE_USGE: pred = LLVMIntUGE; break;
- case TGSI_OPCODE_USLT: pred = LLVMIntULT; break;
- case TGSI_OPCODE_ISGE: pred = LLVMIntSGE; break;
- case TGSI_OPCODE_ISLT: pred = LLVMIntSLT; break;
+ case TGSI_OPCODE_USEQ:
+ case TGSI_OPCODE_U64SEQ: pred = LLVMIntEQ; break;
+ case TGSI_OPCODE_USNE:
+ case TGSI_OPCODE_U64SNE: pred = LLVMIntNE; break;
+ case TGSI_OPCODE_USGE:
+ case TGSI_OPCODE_U64SGE: pred = LLVMIntUGE; break;
+ case TGSI_OPCODE_USLT:
+ case TGSI_OPCODE_U64SLT: pred = LLVMIntULT; break;
+ case TGSI_OPCODE_ISGE:
+ case TGSI_OPCODE_I64SGE: pred = LLVMIntSGE; break;
+ case TGSI_OPCODE_ISLT:
+ case TGSI_OPCODE_I64SLT: pred = LLVMIntSLT; break;
default:
assert(!"unknown instruction");
pred = 0;
@@ -1163,7 +1169,12 @@ static void emit_ssg(
LLVMValueRef cmp, val;
- if (emit_data->inst->Instruction.Opcode == TGSI_OPCODE_ISSG) {
+ if (emit_data->inst->Instruction.Opcode == TGSI_OPCODE_I64SSG) {
+ cmp = LLVMBuildICmp(builder, LLVMIntSGT, emit_data->args[0], bld_base->int64_bld.zero, "");
+ val = LLVMBuildSelect(builder, cmp, bld_base->int64_bld.one, emit_data->args[0], "");
+ cmp = LLVMBuildICmp(builder, LLVMIntSGE, val, bld_base->int64_bld.zero, "");
+ val = LLVMBuildSelect(builder, cmp, val, LLVMConstInt(bld_base->int64_bld.elem_type, -1, true), "");
+ } else if (emit_data->inst->Instruction.Opcode == TGSI_OPCODE_ISSG) {
cmp = LLVMBuildICmp(builder, LLVMIntSGT, emit_data->args[0], bld_base->int_bld.zero, "");
val = LLVMBuildSelect(builder, cmp, bld_base->int_bld.one, emit_data->args[0], "");
cmp = LLVMBuildICmp(builder, LLVMIntSGE, val, bld_base->int_bld.zero, "");
@@ -1434,15 +1445,19 @@ static void emit_minmax_int(const struct lp_build_tgsi_action *action,
default:
assert(0);
case TGSI_OPCODE_IMAX:
+ case TGSI_OPCODE_I64MAX:
op = LLVMIntSGT;
break;
case TGSI_OPCODE_IMIN:
+ case TGSI_OPCODE_I64MIN:
op = LLVMIntSLT;
break;
case TGSI_OPCODE_UMAX:
+ case TGSI_OPCODE_U64MAX:
op = LLVMIntUGT;
break;
case TGSI_OPCODE_UMIN:
+ case TGSI_OPCODE_U64MIN:
op = LLVMIntULT;
break;
}
@@ -1558,6 +1573,18 @@ void radeon_llvm_context_init(struct radeon_llvm_context * ctx, const char *trip
dbl_type.width *= 2;
lp_build_context_init(&ctx->soa.bld_base.dbl_bld, &ctx->gallivm, dbl_type);
}
+ {
+ struct lp_type dtype;
+ dtype = lp_uint_type(type);
+ dtype.width *= 2;
+ lp_build_context_init(&ctx->soa.bld_base.uint64_bld, &ctx->gallivm, dtype);
+ }
+ {
+ struct lp_type dtype;
+ dtype = lp_int_type(type);
+ dtype.width *= 2;
+ lp_build_context_init(&ctx->soa.bld_base.int64_bld, &ctx->gallivm, dtype);
+ }
bld_base->soa = 1;
bld_base->emit_store = radeon_llvm_emit_store;
@@ -1694,6 +1721,26 @@ void radeon_llvm_context_init(struct radeon_llvm_context * ctx, const char *trip
bld_base->op_actions[TGSI_OPCODE_UCMP].emit = emit_ucmp;
bld_base->op_actions[TGSI_OPCODE_UP2H].fetch_args = up2h_fetch_args;
bld_base->op_actions[TGSI_OPCODE_UP2H].emit = emit_up2h;
+
+ bld_base->op_actions[TGSI_OPCODE_I64MAX].emit = emit_minmax_int;
+ bld_base->op_actions[TGSI_OPCODE_I64MIN].emit = emit_minmax_int;
+ bld_base->op_actions[TGSI_OPCODE_U64MAX].emit = emit_minmax_int;
+ bld_base->op_actions[TGSI_OPCODE_U64MIN].emit = emit_minmax_int;
+ bld_base->op_actions[TGSI_OPCODE_I64ABS].emit = emit_iabs;
+ bld_base->op_actions[TGSI_OPCODE_I64SSG].emit = emit_ssg;
+ bld_base->op_actions[TGSI_OPCODE_I64NEG].emit = emit_ineg;
+
+ bld_base->op_actions[TGSI_OPCODE_U64SEQ].emit = emit_icmp;
+ bld_base->op_actions[TGSI_OPCODE_U64SNE].emit = emit_icmp;
+ bld_base->op_actions[TGSI_OPCODE_U64SGE].emit = emit_icmp;
+ bld_base->op_actions[TGSI_OPCODE_U64SLT].emit = emit_icmp;
+ bld_base->op_actions[TGSI_OPCODE_I64SGE].emit = emit_icmp;
+ bld_base->op_actions[TGSI_OPCODE_I64SLT].emit = emit_icmp;
+
+ bld_base->op_actions[TGSI_OPCODE_U64ADD].emit = emit_uadd;
+ bld_base->op_actions[TGSI_OPCODE_U64SHL].emit = emit_shl;
+ bld_base->op_actions[TGSI_OPCODE_U64SHR].emit = emit_ushr;
+ bld_base->op_actions[TGSI_OPCODE_I64SHR].emit = emit_ishr;
}
void radeon_llvm_create_func(struct radeon_llvm_context * ctx,
diff --git a/src/gallium/drivers/radeonsi/si_pipe.c b/src/gallium/drivers/radeonsi/si_pipe.c
index e65a30f..58e554e 100644
--- a/src/gallium/drivers/radeonsi/si_pipe.c
+++ b/src/gallium/drivers/radeonsi/si_pipe.c
@@ -357,6 +357,7 @@ static int si_get_param(struct pipe_screen* pscreen, enum pipe_cap param)
case PIPE_CAP_TGSI_PACK_HALF_FLOAT:
case PIPE_CAP_FRAMEBUFFER_NO_ATTACHMENT:
case PIPE_CAP_ROBUST_BUFFER_ACCESS_BEHAVIOR:
+ case PIPE_CAP_INT64:
return 1;
case PIPE_CAP_RESOURCE_FROM_USER_MEMORY:
--
2.5.5
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