[Mesa-dev] [PATCH 1/4] radeonsi: use conformant line rasterization
Edward O'Callaghan
funfunctor at folklore1984.net
Tue Jun 28 23:39:05 UTC 2016
This series is,
Reviewed-by: Edward O'Callaghan <funfunctor at folklore1984.net>
On 06/29/2016 03:53 AM, Marek Olšák wrote:
> From: Marek Olšák <marek.olsak at amd.com>
>
> AA lines are not completely correct (see TODO), but everything else
> should be.
>
> + 3 linestipple piglits
> ---
> src/gallium/drivers/radeon/cayman_msaa.c | 12 ++++++++++--
> src/gallium/drivers/radeon/r600d_common.h | 6 ++++++
> src/gallium/drivers/radeonsi/si_state.c | 10 +++++++++-
> src/gallium/drivers/radeonsi/si_state_draw.c | 6 ++++--
> 4 files changed, 29 insertions(+), 5 deletions(-)
>
> diff --git a/src/gallium/drivers/radeon/cayman_msaa.c b/src/gallium/drivers/radeon/cayman_msaa.c
> index a9ec4c3..89c4937 100644
> --- a/src/gallium/drivers/radeon/cayman_msaa.c
> +++ b/src/gallium/drivers/radeon/cayman_msaa.c
> @@ -200,6 +200,14 @@ void cayman_emit_msaa_config(struct radeon_winsys_cs *cs, int nr_samples,
> {
> int setup_samples = nr_samples > 1 ? nr_samples :
> overrast_samples > 1 ? overrast_samples : 0;
> + /* Required by OpenGL line rasterization.
> + *
> + * TODO: We should also enable perpendicular endcaps for AA lines,
> + * but that requires implementing line stippling in the pixel
> + * shader. SC can only do line stippling with axis-aligned
> + * endcaps.
> + */
> + unsigned sc_line_cntl = S_028BDC_DX10_DIAMOND_TEST_ENA(1);
>
> if (setup_samples > 1) {
> /* indexed by log2(nr_samples) */
> @@ -215,7 +223,7 @@ void cayman_emit_msaa_config(struct radeon_winsys_cs *cs, int nr_samples,
> util_logbase2(util_next_power_of_two(ps_iter_samples));
>
> radeon_set_context_reg_seq(cs, CM_R_028BDC_PA_SC_LINE_CNTL, 2);
> - radeon_emit(cs, S_028BDC_LAST_PIXEL(1) |
> + radeon_emit(cs, sc_line_cntl |
> S_028BDC_EXPAND_LINE_WIDTH(1)); /* CM_R_028BDC_PA_SC_LINE_CNTL */
> radeon_emit(cs, S_028BE0_MSAA_NUM_SAMPLES(log_samples) |
> S_028BE0_MAX_SAMPLE_DIST(max_dist[log_samples]) |
> @@ -242,7 +250,7 @@ void cayman_emit_msaa_config(struct radeon_winsys_cs *cs, int nr_samples,
> }
> } else {
> radeon_set_context_reg_seq(cs, CM_R_028BDC_PA_SC_LINE_CNTL, 2);
> - radeon_emit(cs, S_028BDC_LAST_PIXEL(1)); /* CM_R_028BDC_PA_SC_LINE_CNTL */
> + radeon_emit(cs, sc_line_cntl); /* CM_R_028BDC_PA_SC_LINE_CNTL */
> radeon_emit(cs, 0); /* CM_R_028BE0_PA_SC_AA_CONFIG */
>
> radeon_set_context_reg(cs, CM_R_028804_DB_EQAA,
> diff --git a/src/gallium/drivers/radeon/r600d_common.h b/src/gallium/drivers/radeon/r600d_common.h
> index e50de96..6f534b3 100644
> --- a/src/gallium/drivers/radeon/r600d_common.h
> +++ b/src/gallium/drivers/radeon/r600d_common.h
> @@ -203,6 +203,12 @@
> #define S_028BDC_LAST_PIXEL(x) (((unsigned)(x) & 0x1) << 10)
> #define G_028BDC_LAST_PIXEL(x) (((x) >> 10) & 0x1)
> #define C_028BDC_LAST_PIXEL 0xFFFFFBFF
> +#define S_028BDC_PERPENDICULAR_ENDCAP_ENA(x) (((unsigned)(x) & 0x1) << 11)
> +#define G_028BDC_PERPENDICULAR_ENDCAP_ENA(x) (((x) >> 11) & 0x1)
> +#define C_028BDC_PERPENDICULAR_ENDCAP_ENA 0xFFFFF7FF
> +#define S_028BDC_DX10_DIAMOND_TEST_ENA(x) (((unsigned)(x) & 0x1) << 12)
> +#define G_028BDC_DX10_DIAMOND_TEST_ENA(x) (((x) >> 12) & 0x1)
> +#define C_028BDC_DX10_DIAMOND_TEST_ENA 0xFFFFEFFF
> #define CM_R_028BE0_PA_SC_AA_CONFIG 0x28be0
> #define S_028BE0_MSAA_NUM_SAMPLES(x) (((unsigned)(x) & 0x7) << 0)
> #define S_028BE0_AA_MASK_CENTROID_DTMN(x) (((unsigned)(x) & 0x1) << 4)
> diff --git a/src/gallium/drivers/radeonsi/si_state.c b/src/gallium/drivers/radeonsi/si_state.c
> index 0a2fdbf..b21fa5c 100644
> --- a/src/gallium/drivers/radeonsi/si_state.c
> +++ b/src/gallium/drivers/radeonsi/si_state.c
> @@ -3805,7 +3805,15 @@ static void si_init_config(struct si_context *sctx)
> S_028034_BR_X(16384) | S_028034_BR_Y(16384));
>
> si_pm4_set_reg(pm4, R_02820C_PA_SC_CLIPRECT_RULE, 0xFFFF);
> - si_pm4_set_reg(pm4, R_028230_PA_SC_EDGERULE, 0xAAAAAAAA);
> + si_pm4_set_reg(pm4, R_028230_PA_SC_EDGERULE,
> + S_028230_ER_TRI(0xA) |
> + S_028230_ER_POINT(0xA) |
> + S_028230_ER_RECT(0xA) |
> + /* Required by DX10_DIAMOND_TEST_ENA: */
> + S_028230_ER_LINE_LR(0x1A) |
> + S_028230_ER_LINE_RL(0x26) |
> + S_028230_ER_LINE_TB(0xA) |
> + S_028230_ER_LINE_BT(0xA));
> /* PA_SU_HARDWARE_SCREEN_OFFSET must be 0 due to hw bug on SI */
> si_pm4_set_reg(pm4, R_028234_PA_SU_HARDWARE_SCREEN_OFFSET, 0);
> si_pm4_set_reg(pm4, R_028820_PA_CL_NANINF_CNTL, 0);
> diff --git a/src/gallium/drivers/radeonsi/si_state_draw.c b/src/gallium/drivers/radeonsi/si_state_draw.c
> index 5f866d5..b9a7c14 100644
> --- a/src/gallium/drivers/radeonsi/si_state_draw.c
> +++ b/src/gallium/drivers/radeonsi/si_state_draw.c
> @@ -429,10 +429,12 @@ static void si_emit_rasterizer_prim_state(struct si_context *sctx)
> rs->pa_sc_line_stipple == sctx->last_sc_line_stipple)
> return;
>
> + /* For lines, reset the stipple pattern at each primitive. Otherwise,
> + * reset the stipple pattern at each packet (line strips, line loops).
> + */
> radeon_set_context_reg(cs, R_028A0C_PA_SC_LINE_STIPPLE,
> rs->pa_sc_line_stipple |
> - S_028A0C_AUTO_RESET_CNTL(rast_prim == PIPE_PRIM_LINES ? 1 :
> - rast_prim == PIPE_PRIM_LINE_STRIP ? 2 : 0));
> + S_028A0C_AUTO_RESET_CNTL(rast_prim == PIPE_PRIM_LINES ? 1 : 2));
>
> sctx->last_rast_prim = rast_prim;
> sctx->last_sc_line_stipple = rs->pa_sc_line_stipple;
>
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