[Mesa-dev] [PATCH] radeonsi: lower SQRT to RSQ+RCP to fix the game Risen

Marek Olšák maraeo at gmail.com
Mon May 30 23:19:41 UTC 2016


From: Marek Olšák <marek.olsak at amd.com>

Sadly, I haven't been able to find any other way to fix the bug
for radeonsi. The game seems to expect DX9 behavior.

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=94627
(against nouveau)
---
 .../drivers/radeon/radeon_setup_tgsi_llvm.c        | 22 ++++++++++++++++++++--
 1 file changed, 20 insertions(+), 2 deletions(-)

diff --git a/src/gallium/drivers/radeon/radeon_setup_tgsi_llvm.c b/src/gallium/drivers/radeon/radeon_setup_tgsi_llvm.c
index 74b36ec..c84c850 100644
--- a/src/gallium/drivers/radeon/radeon_setup_tgsi_llvm.c
+++ b/src/gallium/drivers/radeon/radeon_setup_tgsi_llvm.c
@@ -1522,6 +1522,25 @@ static void emit_up2h(const struct lp_build_tgsi_action *action,
 	}
 }
 
+static void emit_sqrt(const struct lp_build_tgsi_action *action,
+		      struct lp_build_tgsi_context * bld_base,
+		      struct lp_build_emit_data * emit_data)
+{
+	LLVMBuilderRef builder = bld_base->base.gallivm->builder;
+	LLVMValueRef arg = emit_data->args[0];
+
+	/* The game "Risen" renders correctly only if RSQ + RCP is used to
+	 * implement SQRT.
+	 */
+	arg = lp_build_intrinsic(builder, "llvm.AMDGPU.rsq.f32",
+				 emit_data->dst_type, &arg, 1,
+				 LLVMReadNoneAttribute);
+
+	arg = LLVMBuildFDiv(builder, bld_base->base.one, arg, "");
+	emit_data->output[emit_data->chan] = arg;
+	return;
+}
+
 void radeon_llvm_context_init(struct radeon_llvm_context * ctx, const char *triple)
 {
 	struct lp_type type;
@@ -1671,8 +1690,7 @@ void radeon_llvm_context_init(struct radeon_llvm_context * ctx, const char *trip
 	bld_base->op_actions[TGSI_OPCODE_SGT].emit = emit_set_cond;
 	bld_base->op_actions[TGSI_OPCODE_SIN].emit = build_tgsi_intrinsic_nomem;
 	bld_base->op_actions[TGSI_OPCODE_SIN].intr_name = "llvm.sin.f32";
-	bld_base->op_actions[TGSI_OPCODE_SQRT].emit = build_tgsi_intrinsic_nomem;
-	bld_base->op_actions[TGSI_OPCODE_SQRT].intr_name = "llvm.sqrt.f32";
+	bld_base->op_actions[TGSI_OPCODE_SQRT].emit = emit_sqrt;
 	bld_base->op_actions[TGSI_OPCODE_SSG].emit = emit_ssg;
 	bld_base->op_actions[TGSI_OPCODE_TRUNC].emit = build_tgsi_intrinsic_nomem;
 	bld_base->op_actions[TGSI_OPCODE_TRUNC].intr_name = "llvm.trunc.f32";
-- 
2.7.4



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