[Mesa-dev] [PATCH 08/24] gallium/radeon: define RADEON_SURF_MODE_* as enums

[Marek Olšák]

From: Marek Olšák <marek.olsak at amd.com>

---
 src/gallium/drivers/radeon/r600_texture.c  | 12 +++++++-----
 src/gallium/drivers/radeon/radeon_winsys.h | 11 +++++++----
 2 files changed, 14 insertions(+), 9 deletions(-)

diff --git a/src/gallium/drivers/radeon/r600_texture.c b/src/gallium/drivers/radeon/r600_texture.c
index ca67125..daa743e 100644
--- a/src/gallium/drivers/radeon/r600_texture.c
+++ b/src/gallium/drivers/radeon/r600_texture.c
@@ -30,22 +30,23 @@
 #include "util/u_format.h"
 #include "util/u_memory.h"
 #include "util/u_pack_color.h"
 #include "util/u_surface.h"
 #include "os/os_time.h"
 #include <errno.h>
 #include <inttypes.h>
 
 static void r600_texture_discard_cmask(struct r600_common_screen *rscreen,
 				       struct r600_texture *rtex);
-static unsigned r600_choose_tiling(struct r600_common_screen *rscreen,
-				   const struct pipe_resource *templ);
+static enum radeon_surf_mode
+r600_choose_tiling(struct r600_common_screen *rscreen,
+		   const struct pipe_resource *templ);
 
 
 bool r600_prepare_for_dma_blit(struct r600_common_context *rctx,
 			       struct r600_texture *rdst,
 			       unsigned dst_level, unsigned dstx,
 			       unsigned dsty, unsigned dstz,
 			       struct r600_texture *rsrc,
 			       unsigned src_level,
 			       const struct pipe_box *src_box)
 {
@@ -184,21 +185,21 @@ static unsigned r600_texture_get_offset(struct r600_texture *rtex, unsigned leve
 
 	return rtex->surface.level[level].offset +
 	       box->z * rtex->surface.level[level].slice_size +
 	       box->y / util_format_get_blockheight(format) * rtex->surface.level[level].pitch_bytes +
 	       box->x / util_format_get_blockwidth(format) * util_format_get_blocksize(format);
 }
 
 static int r600_init_surface(struct r600_common_screen *rscreen,
 			     struct radeon_surf *surface,
 			     const struct pipe_resource *ptex,
-			     unsigned array_mode,
+			     enum radeon_surf_mode array_mode,
 			     unsigned pitch_in_bytes_override,
 			     unsigned offset,
 			     bool is_imported,
 			     bool is_scanout,
 			     bool is_flushed_depth,
 			     bool tc_compatible_htile)
 {
 	const struct util_format_description *desc =
 		util_format_description(ptex->format);
 	bool is_depth, is_stencil;
@@ -1193,22 +1194,23 @@ r600_texture_create_object(struct pipe_screen *screen,
 
 	if (rscreen->debug_flags & DBG_TEX) {
 		puts("Texture:");
 		r600_print_texture_info(rtex, stdout);
 		fflush(stdout);
 	}
 
 	return rtex;
 }
 
-static unsigned r600_choose_tiling(struct r600_common_screen *rscreen,
-				   const struct pipe_resource *templ)
+static enum radeon_surf_mode
+r600_choose_tiling(struct r600_common_screen *rscreen,
+		   const struct pipe_resource *templ)
 {
 	const struct util_format_description *desc = util_format_description(templ->format);
 	bool force_tiling = templ->flags & R600_RESOURCE_FLAG_FORCE_TILING;
 
 	/* MSAA resources must be 2D tiled. */
 	if (templ->nr_samples > 1)
 		return RADEON_SURF_MODE_2D;
 
 	/* Transfer resources should be linear. */
 	if (templ->flags & R600_RESOURCE_FLAG_TRANSFER)
diff --git a/src/gallium/drivers/radeon/radeon_winsys.h b/src/gallium/drivers/radeon/radeon_winsys.h
index 75badd0..3bd141e 100644
--- a/src/gallium/drivers/radeon/radeon_winsys.h
+++ b/src/gallium/drivers/radeon/radeon_winsys.h
@@ -250,33 +250,36 @@ struct radeon_bo_metadata {
     uint32_t                metadata[64];
 };
 
 enum radeon_feature_id {
     RADEON_FID_R300_HYPERZ_ACCESS,     /* ZMask + HiZ */
     RADEON_FID_R300_CMASK_ACCESS,
 };
 
 #define RADEON_SURF_MAX_LEVEL                   32
 
+enum radeon_surf_mode {
+    RADEON_SURF_MODE_LINEAR_ALIGNED = 1,
+    RADEON_SURF_MODE_1D = 2,
+    RADEON_SURF_MODE_2D = 3,
+};
+
 #define RADEON_SURF_TYPE_MASK                   0xFF
 #define RADEON_SURF_TYPE_SHIFT                  0
 #define     RADEON_SURF_TYPE_1D                     0
 #define     RADEON_SURF_TYPE_2D                     1
 #define     RADEON_SURF_TYPE_3D                     2
 #define     RADEON_SURF_TYPE_CUBEMAP                3
 #define     RADEON_SURF_TYPE_1D_ARRAY               4
 #define     RADEON_SURF_TYPE_2D_ARRAY               5
 #define RADEON_SURF_MODE_MASK                   0xFF
 #define RADEON_SURF_MODE_SHIFT                  8
-#define     RADEON_SURF_MODE_LINEAR_ALIGNED         1
-#define     RADEON_SURF_MODE_1D                     2
-#define     RADEON_SURF_MODE_2D                     3
 #define RADEON_SURF_SCANOUT                     (1 << 16)
 #define RADEON_SURF_ZBUFFER                     (1 << 17)
 #define RADEON_SURF_SBUFFER                     (1 << 18)
 #define RADEON_SURF_Z_OR_SBUFFER                (RADEON_SURF_ZBUFFER | RADEON_SURF_SBUFFER)
 #define RADEON_SURF_HAS_SBUFFER_MIPTREE         (1 << 19)
 #define RADEON_SURF_HAS_TILE_MODE_INDEX         (1 << 20)
 #define RADEON_SURF_FMASK                       (1 << 21)
 #define RADEON_SURF_DISABLE_DCC                 (1 << 22)
 #define RADEON_SURF_TC_COMPATIBLE_HTILE         (1 << 23)
 #define RADEON_SURF_IMPORTED                    (1 << 24)
@@ -288,21 +291,21 @@ enum radeon_feature_id {
 struct radeon_surf_level {
     uint64_t                    offset;
     uint64_t                    slice_size;
     uint32_t                    npix_x;
     uint32_t                    npix_y;
     uint32_t                    npix_z;
     uint32_t                    nblk_x;
     uint32_t                    nblk_y;
     uint32_t                    nblk_z;
     uint32_t                    pitch_bytes;
-    uint32_t                    mode;
+    enum radeon_surf_mode       mode;
     uint64_t                    dcc_offset;
     uint64_t                    dcc_fast_clear_size;
     bool                        dcc_enabled;
 };
 
 struct radeon_surf {
     /* These are inputs to the calculator. */
     uint32_t                    npix_x;
     uint32_t                    npix_y;
     uint32_t                    npix_z;
-- 
2.7.4