[Mesa-dev] [PATCH 18/24] gallium/radeon: print tiling index when printing texture info

[Marek Olšák]

From: Marek Olšák <marek.olsak at amd.com>

---
 src/gallium/drivers/radeon/r600_texture.c | 10 ++++++----
 1 file changed, 6 insertions(+), 4 deletions(-)

diff --git a/src/gallium/drivers/radeon/r600_texture.c b/src/gallium/drivers/radeon/r600_texture.c
index ca82a74..2f2c17c 100644
--- a/src/gallium/drivers/radeon/r600_texture.c
+++ b/src/gallium/drivers/radeon/r600_texture.c
@@ -949,48 +949,50 @@ void r600_print_texture_info(struct r600_texture *rtex, FILE *f)
 			fprintf(f, "  DCCLevel[%i]: enabled=%u, offset=%"PRIu64", "
 				"fast_clear_size=%"PRIu64"\n",
 				i, rtex->surface.level[i].dcc_enabled,
 				rtex->surface.level[i].dcc_offset,
 				rtex->surface.level[i].dcc_fast_clear_size);
 	}
 
 	for (i = 0; i <= rtex->resource.b.b.last_level; i++)
 		fprintf(f, "  Level[%i]: offset=%"PRIu64", slice_size=%"PRIu64", "
 			"npix_x=%u, npix_y=%u, npix_z=%u, nblk_x=%u, nblk_y=%u, "
-			"pitch_bytes=%u, mode=%u\n",
+			"pitch_bytes=%u, mode=%u, tiling_index = %u\n",
 			i, rtex->surface.level[i].offset,
 			rtex->surface.level[i].slice_size,
 			u_minify(rtex->resource.b.b.width0, i),
 			u_minify(rtex->resource.b.b.height0, i),
 			u_minify(rtex->resource.b.b.depth0, i),
 			rtex->surface.level[i].nblk_x,
 			rtex->surface.level[i].nblk_y,
 			rtex->surface.level[i].pitch_bytes,
-			rtex->surface.level[i].mode);
+			rtex->surface.level[i].mode,
+			rtex->surface.tiling_index[i]);
 
 	if (rtex->surface.flags & RADEON_SURF_SBUFFER) {
 		fprintf(f, "  StencilLayout: tilesplit=%u\n",
 			rtex->surface.stencil_tile_split);
 		for (i = 0; i <= rtex->resource.b.b.last_level; i++) {
 			fprintf(f, "  StencilLevel[%i]: offset=%"PRIu64", "
 				"slice_size=%"PRIu64", npix_x=%u, "
 				"npix_y=%u, npix_z=%u, nblk_x=%u, nblk_y=%u, "
-				"pitch_bytes=%u, mode=%u\n",
+				"pitch_bytes=%u, mode=%u, tiling_index = %u\n",
 				i, rtex->surface.stencil_level[i].offset,
 				rtex->surface.stencil_level[i].slice_size,
 				u_minify(rtex->resource.b.b.width0, i),
 				u_minify(rtex->resource.b.b.height0, i),
 				u_minify(rtex->resource.b.b.depth0, i),
 				rtex->surface.stencil_level[i].nblk_x,
 				rtex->surface.stencil_level[i].nblk_y,
 				rtex->surface.stencil_level[i].pitch_bytes,
-				rtex->surface.stencil_level[i].mode);
+				rtex->surface.stencil_level[i].mode,
+				rtex->surface.stencil_tiling_index[i]);
 		}
 	}
 }
 
 /* Common processing for r600_texture_create and r600_texture_from_handle */
 static struct r600_texture *
 r600_texture_create_object(struct pipe_screen *screen,
 			   const struct pipe_resource *base,
 			   struct pb_buffer *buf,
 			   struct radeon_surf *surface)
-- 
2.7.4