[Mesa-dev] [PATCH 13/16] i965/blorp: Use conditional end-of-pipe-sync

[Topi Pohjolainen]

instead of unconditional render cache flush.

Signed-off-by: Topi Pohjolainen <topi.pohjolainen at intel.com>
---
 src/mesa/drivers/dri/i965/brw_blorp.c | 23 ++++++++++++++++-------
 1 file changed, 16 insertions(+), 7 deletions(-)

diff --git a/src/mesa/drivers/dri/i965/brw_blorp.c b/src/mesa/drivers/dri/i965/brw_blorp.c
index e3e4402..bc9f964 100644
--- a/src/mesa/drivers/dri/i965/brw_blorp.c
+++ b/src/mesa/drivers/dri/i965/brw_blorp.c
@@ -367,11 +367,13 @@ prepare_blit(struct brw_context *brw,
              struct intel_mipmap_tree *dst_mt,
              unsigned dst_level, unsigned dst_layer, uint32_t dst_usage_flags)
 {
-   prepare_hiz_for_blit(brw, src_mt, src_level, src_layer, false);
-   prepare_hiz_for_blit(brw, dst_mt, dst_level, dst_layer, true);
-
-   prepare_ccs_for_blit(brw, src_mt, src_level, src_layer, src_usage_flags);
-   prepare_ccs_for_blit(brw, dst_mt, dst_level, dst_layer, dst_usage_flags);
+   const bool needs_sync =
+      prepare_hiz_for_blit(brw, src_mt, src_level, src_layer, false) |
+      prepare_hiz_for_blit(brw, dst_mt, dst_level, dst_layer, true) |
+      prepare_ccs_for_blit(brw, src_mt, src_level, src_layer,
+                           src_usage_flags) |
+      prepare_ccs_for_blit(brw, dst_mt, dst_level, dst_layer,
+                           dst_usage_flags);
 
    /* Flush the sampler and render caches.  We definitely need to flush the
     * sampler cache so that we get updated contents from the render cache for
@@ -380,8 +382,15 @@ prepare_blit(struct brw_context *brw,
     * data with different formats, which blorp does for stencil and depth
     * data.
     */
-   brw_render_cache_set_check_flush(brw, src_mt->bo);
-   brw_render_cache_set_check_flush(brw, dst_mt->bo);
+   if (needs_sync) {
+      brw_end_of_pipe_sync(brw);
+      brw_render_cache_set_clear(brw);
+   } else if (_mesa_set_search(brw->render_cache, src_mt->bo)) {
+      brw_emit_pipe_control_flush(brw,
+                                  PIPE_CONTROL_RENDER_TARGET_FLUSH |
+                                  PIPE_CONTROL_CS_STALL);
+      brw_render_cache_set_clear(brw);
+   }
 
    brw_emit_pipe_control_flush(brw,
                                PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE);
-- 
2.5.5