[Mesa-dev] [PATCH 05/14] ac/surface: increment surf_index only when tile swizzle is allowed

[Marek Olšák]

From: Marek Olšák <marek.olsak at amd.com>

---
 src/amd/common/ac_surface.c                    | 6 ++++--
 src/amd/common/ac_surface.h                    | 2 +-
 src/amd/vulkan/radv_image.c                    | 2 +-
 src/gallium/winsys/amdgpu/drm/amdgpu_surface.c | 1 +
 4 files changed, 7 insertions(+), 4 deletions(-)

diff --git a/src/amd/common/ac_surface.c b/src/amd/common/ac_surface.c
index 61b4e41..68700f4 100644
--- a/src/amd/common/ac_surface.c
+++ b/src/amd/common/ac_surface.c
@@ -23,20 +23,21 @@
  * The above copyright notice and this permission notice (including the
  * next paragraph) shall be included in all copies or substantial portions
  * of the Software.
  */
 
 #include "ac_surface.h"
 #include "amd_family.h"
 #include "amdgpu_id.h"
 #include "ac_gpu_info.h"
 #include "util/macros.h"
+#include "util/u_atomic.h"
 #include "util/u_math.h"
 
 #include <errno.h>
 #include <stdio.h>
 #include <stdlib.h>
 #include <amdgpu.h>
 #include <amdgpu_drm.h>
 
 #include "addrlib/addrinterface.h"
 
@@ -699,27 +700,28 @@ static int gfx6_compute_surface(ADDR_HANDLE addrlib,
 
 	/* Make sure HTILE covers the whole miptree, because the shader reads
 	 * TC-compatible HTILE even for levels where it's disabled by DB.
 	 */
 	if (surf->htile_size && config->info.levels > 1)
 		surf->htile_size *= 2;
 
 	surf->is_linear = surf->u.legacy.level[0].mode == RADEON_SURF_MODE_LINEAR_ALIGNED;
 
 	/* Work out tile swizzle. */
-	if (surf->u.legacy.level[0].mode == RADEON_SURF_MODE_2D &&
+	if (config->info.surf_index &&
+	    surf->u.legacy.level[0].mode == RADEON_SURF_MODE_2D &&
 	    !(surf->flags & (RADEON_SURF_Z_OR_SBUFFER | RADEON_SURF_SHAREABLE)) &&
 	    (config->info.samples > 1 || !(surf->flags & RADEON_SURF_SCANOUT))) {
 		ADDR_COMPUTE_BASE_SWIZZLE_INPUT AddrBaseSwizzleIn = {0};
 		ADDR_COMPUTE_BASE_SWIZZLE_OUTPUT AddrBaseSwizzleOut = {0};
 
-		AddrBaseSwizzleIn.surfIndex = config->info.surf_index;
+		AddrBaseSwizzleIn.surfIndex = p_atomic_inc_return(config->info.surf_index) - 1;
 		AddrBaseSwizzleIn.tileIndex = AddrSurfInfoIn.tileIndex;
 		AddrBaseSwizzleIn.macroModeIndex = AddrSurfInfoOut.macroModeIndex;
 		AddrBaseSwizzleIn.pTileInfo = AddrSurfInfoOut.pTileInfo;
 		AddrBaseSwizzleIn.tileMode = AddrSurfInfoOut.tileMode;
 		AddrComputeBaseSwizzle(addrlib, &AddrBaseSwizzleIn, &AddrBaseSwizzleOut);
 
 		assert(AddrBaseSwizzleOut.tileSwizzle <=
 		       u_bit_consecutive(0, sizeof(surf->tile_swizzle) * 8));
 		surf->tile_swizzle = AddrBaseSwizzleOut.tileSwizzle;
 	}
diff --git a/src/amd/common/ac_surface.h b/src/amd/common/ac_surface.h
index 01a71f3..b2620f9 100644
--- a/src/amd/common/ac_surface.h
+++ b/src/amd/common/ac_surface.h
@@ -202,24 +202,24 @@ struct radeon_surf {
 
         /* GFX9+ return values. */
         struct gfx9_surf_layout gfx9;
     } u;
 };
 
 struct ac_surf_info {
 	uint32_t width;
 	uint32_t height;
 	uint32_t depth;
-	uint32_t surf_index;
 	uint8_t samples;
 	uint8_t levels;
 	uint16_t array_size;
+	uint32_t *surf_index; /* Set a monotonic counter for tile swizzling. */
 };
 
 struct ac_surf_config {
 	struct ac_surf_info info;
 	unsigned is_3d : 1;
 	unsigned is_cube : 1;
 };
 
 ADDR_HANDLE amdgpu_addr_create(const struct radeon_info *info,
 			       const struct amdgpu_gpu_info *amdinfo,
diff --git a/src/amd/vulkan/radv_image.c b/src/amd/vulkan/radv_image.c
index 499287d..8456d3a 100644
--- a/src/amd/vulkan/radv_image.c
+++ b/src/amd/vulkan/radv_image.c
@@ -802,21 +802,21 @@ radv_image_create(VkDevice _device,
 		for (uint32_t i = 0; i < pCreateInfo->queueFamilyIndexCount; ++i)
 			if (pCreateInfo->pQueueFamilyIndices[i] == VK_QUEUE_FAMILY_EXTERNAL_KHR)
 				image->queue_family_mask |= (1u << RADV_MAX_QUEUE_FAMILIES) - 1u;
 			else
 				image->queue_family_mask |= 1u << pCreateInfo->pQueueFamilyIndices[i];
 	}
 
 	image->shareable = vk_find_struct_const(pCreateInfo->pNext,
 	                                        EXTERNAL_MEMORY_IMAGE_CREATE_INFO_KHR) != NULL;
 	if (!vk_format_is_depth(pCreateInfo->format) && !create_info->scanout && !image->shareable) {
-		image->info.surf_index = p_atomic_inc_return(&device->image_mrt_offset_counter) - 1;
+		image->info.surf_index = &device->image_mrt_offset_counter;
 	}
 
 	radv_init_surface(device, &image->surface, create_info);
 
 	device->ws->surface_init(device->ws, &image->info, &image->surface);
 
 	image->size = image->surface.surf_size;
 	image->alignment = image->surface.surf_alignment;
 
 	if (image->exclusive || image->queue_family_mask == 1)
diff --git a/src/gallium/winsys/amdgpu/drm/amdgpu_surface.c b/src/gallium/winsys/amdgpu/drm/amdgpu_surface.c
index 1a2b7c4..d438b6d 100644
--- a/src/gallium/winsys/amdgpu/drm/amdgpu_surface.c
+++ b/src/gallium/winsys/amdgpu/drm/amdgpu_surface.c
@@ -85,18 +85,19 @@ static int amdgpu_surface_init(struct radeon_winsys *rws,
    struct ac_surf_config config;
 
    config.info.width = tex->width0;
    config.info.height = tex->height0;
    config.info.depth = tex->depth0;
    config.info.array_size = tex->array_size;
    config.info.samples = tex->nr_samples;
    config.info.levels = tex->last_level + 1;
    config.is_3d = !!(tex->target == PIPE_TEXTURE_3D);
    config.is_cube = !!(tex->target == PIPE_TEXTURE_CUBE);
+   config.info.surf_index = NULL;
 
    return ac_compute_surface(ws->addrlib, &ws->info, &config, mode, surf);
 }
 
 void amdgpu_surface_init_functions(struct amdgpu_winsys *ws)
 {
    ws->base.surface_init = amdgpu_surface_init;
 }
-- 
2.7.4