[Mesa-dev] [PATCH 15/17] mesa/st: handle indirect indexing of asm programs for backends that pack uniforms

[Timothy Arceri]

Currently asm programs don't support packing and are always padded to 4.
---
 src/mesa/state_tracker/st_mesa_to_tgsi.c | 22 +++++++++++++---------
 1 file changed, 13 insertions(+), 9 deletions(-)

diff --git a/src/mesa/state_tracker/st_mesa_to_tgsi.c b/src/mesa/state_tracker/st_mesa_to_tgsi.c
index 83dbabd..80248fe 100644
--- a/src/mesa/state_tracker/st_mesa_to_tgsi.c
+++ b/src/mesa/state_tracker/st_mesa_to_tgsi.c
@@ -277,22 +277,22 @@ translate_dst( struct st_translate *t,
       dst = ureg_dst_indirect( dst, ureg_src(t->address[0]) );
 
    return dst;
 }
 
 
 /**
  * Create a TGSI ureg_src register from a Mesa src register.
  */
 static struct ureg_src
-translate_src( struct st_translate *t,
-               const struct prog_src_register *SrcReg )
+translate_src(struct gl_context *ctx, struct st_translate *t,
+              const struct prog_src_register *SrcReg)
 {
    struct ureg_src src = src_register( t, SrcReg->File, SrcReg->Index );
 
    src = ureg_swizzle( src,
                        GET_SWZ( SrcReg->Swizzle, 0 ) & 0x3,
                        GET_SWZ( SrcReg->Swizzle, 1 ) & 0x3,
                        GET_SWZ( SrcReg->Swizzle, 2 ) & 0x3,
                        GET_SWZ( SrcReg->Swizzle, 3 ) & 0x3);
 
    if (SrcReg->Negate == NEGATE_XYZW)
@@ -300,21 +300,25 @@ translate_src( struct st_translate *t,
 
    if (SrcReg->RelAddr) {
       src = ureg_src_indirect( src, ureg_src(t->address[0]));
       if (SrcReg->File != PROGRAM_INPUT &&
           SrcReg->File != PROGRAM_OUTPUT) {
          /* If SrcReg->Index was negative, it was set to zero in
           * src_register().  Reassign it now.  But don't do this
           * for input/output regs since they get remapped while
           * const buffers don't.
           */
-         src.Index = SrcReg->Index;
+         if (ctx->Const.PackedDriverUniformStorage) {
+            src.Index = SrcReg->Index * 4;
+         } else {
+            src.Index = SrcReg->Index;
+         }
       }
    }
 
    return src;
 }
 
 
 static struct ureg_src swizzle_4v( struct ureg_src src,
                                    const unsigned *swz )
 {
@@ -324,23 +328,23 @@ static struct ureg_src swizzle_4v( struct ureg_src src,
 
 /**
  * Translate a SWZ instruction into a MOV, MUL or MAD instruction.  EG:
  *
  *   SWZ dst, src.x-y10 
  * 
  * becomes:
  *
  *   MAD dst {1,-1,0,0}, src.xyxx, {0,0,1,0}
  */
-static void emit_swz( struct st_translate *t,
-                      struct ureg_dst dst,
-                      const struct prog_src_register *SrcReg )
+static void emit_swz(struct gl_context *ctx, struct st_translate *t,
+                     struct ureg_dst dst,
+                     const struct prog_src_register *SrcReg)
 {
    struct ureg_program *ureg = t->ureg;
    struct ureg_src src = src_register( t, SrcReg->File, SrcReg->Index );
 
    unsigned negate_mask =  SrcReg->Negate;
 
    unsigned one_mask = ((GET_SWZ(SrcReg->Swizzle, 0) == SWIZZLE_ONE) << 0 |
                         (GET_SWZ(SrcReg->Swizzle, 1) == SWIZZLE_ONE) << 1 |
                         (GET_SWZ(SrcReg->Swizzle, 2) == SWIZZLE_ONE) << 2 |
                         (GET_SWZ(SrcReg->Swizzle, 3) == SWIZZLE_ONE) << 3);
@@ -363,21 +367,21 @@ static void emit_swz( struct st_translate *t,
 
    if (dst.WriteMask == 0)
       return;
 
    /* Is this just a MOV?
     */
    if (zero_mask == 0 &&
        one_mask == 0 &&
        (negate_mask == 0 || negate_mask == TGSI_WRITEMASK_XYZW)) 
    {
-      ureg_MOV( ureg, dst, translate_src( t, SrcReg ));
+      ureg_MOV(ureg, dst, translate_src(ctx, t, SrcReg));
       return;
    }
 
 #define IMM_ZERO    0
 #define IMM_ONE     1
 #define IMM_NEG_ONE 2
 
    imm = ureg_imm3f( ureg, 0, 1, -1 );
 
    for (i = 0; i < 4; i++) {
@@ -533,25 +537,25 @@ compile_instruction(
 
    num_dst = _mesa_num_inst_dst_regs( inst->Opcode );
    num_src = _mesa_num_inst_src_regs( inst->Opcode );
 
    if (num_dst) 
       dst[0] = translate_dst( t, 
                               &inst->DstReg,
                               inst->Saturate);
 
    for (i = 0; i < num_src; i++) 
-      src[i] = translate_src( t, &inst->SrcReg[i] );
+      src[i] = translate_src(ctx, t, &inst->SrcReg[i]);
 
    switch( inst->Opcode ) {
    case OPCODE_SWZ:
-      emit_swz( t, dst[0], &inst->SrcReg[0] );
+      emit_swz(ctx, t, dst[0], &inst->SrcReg[0]);
       return;
 
    case OPCODE_TEX:
    case OPCODE_TXB:
    case OPCODE_TXP:
       src[num_src++] = t->samplers[inst->TexSrcUnit];
       ureg_tex_insn( ureg,
                      translate_opcode( inst->Opcode ),
                      dst, num_dst, 
                      st_translate_texture_target( inst->TexSrcTarget,
-- 
2.9.4