[Mesa-dev] [PATCH 082/140] radeonsi/gfx9: ELEMENT_SIZE change

[Marek Olšák]

From: Marek Olšák <marek.olsak at amd.com>

---
 src/gallium/drivers/radeonsi/si_compute.c     | 16 ++++++++++------
 src/gallium/drivers/radeonsi/si_descriptors.c |  6 +++++-
 2 files changed, 15 insertions(+), 7 deletions(-)

diff --git a/src/gallium/drivers/radeonsi/si_compute.c b/src/gallium/drivers/radeonsi/si_compute.c
index 19a9189..2cf96d6 100644
--- a/src/gallium/drivers/radeonsi/si_compute.c
+++ b/src/gallium/drivers/radeonsi/si_compute.c
@@ -461,30 +461,34 @@ static void setup_scratch_rsrc_user_sgprs(struct si_context *sctx,
 			AMD_CODE_PROPERTY_PRIVATE_ELEMENT_SIZE);
 
 	uint32_t scratch_dword0 = scratch_va & 0xffffffff;
 	uint32_t scratch_dword1 =
 		S_008F04_BASE_ADDRESS_HI(scratch_va >> 32) |
 		S_008F04_SWIZZLE_ENABLE(1);
 
 	/* Disable address clamping */
 	uint32_t scratch_dword2 = 0xffffffff;
 	uint32_t scratch_dword3 =
-		S_008F0C_ELEMENT_SIZE(max_private_element_size) |
 		S_008F0C_INDEX_STRIDE(3) |
 		S_008F0C_ADD_TID_ENABLE(1);
 
+	if (sctx->b.chip_class >= GFX9) {
+		assert(max_private_element_size == 1); /* always 4 bytes on GFX9 */
+	} else {
+		scratch_dword3 |= S_008F0C_ELEMENT_SIZE(max_private_element_size);
 
-	if (sctx->screen->b.chip_class < VI) {
-		/* BUF_DATA_FORMAT is ignored, but it cannot be
-		   BUF_DATA_FORMAT_INVALID. */
-		scratch_dword3 |=
-			S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_8);
+		if (sctx->b.chip_class < VI) {
+			/* BUF_DATA_FORMAT is ignored, but it cannot be
+			 * BUF_DATA_FORMAT_INVALID. */
+			scratch_dword3 |=
+				S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_8);
+		}
 	}
 
 	radeon_set_sh_reg_seq(cs, R_00B900_COMPUTE_USER_DATA_0 +
 							(user_sgpr * 4), 4);
 	radeon_emit(cs, scratch_dword0);
 	radeon_emit(cs, scratch_dword1);
 	radeon_emit(cs, scratch_dword2);
 	radeon_emit(cs, scratch_dword3);
 }
 
diff --git a/src/gallium/drivers/radeonsi/si_descriptors.c b/src/gallium/drivers/radeonsi/si_descriptors.c
index c13bc94..71b511c 100644
--- a/src/gallium/drivers/radeonsi/si_descriptors.c
+++ b/src/gallium/drivers/radeonsi/si_descriptors.c
@@ -1324,24 +1324,28 @@ void si_set_ring_buffer(struct pipe_context *ctx, uint slot,
 		desc[1] = S_008F04_BASE_ADDRESS_HI(va >> 32) |
 			  S_008F04_STRIDE(stride) |
 			  S_008F04_SWIZZLE_ENABLE(swizzle);
 		desc[2] = num_records;
 		desc[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
 			  S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
 			  S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
 			  S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
 			  S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
 			  S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32) |
-			  S_008F0C_ELEMENT_SIZE(element_size) |
 			  S_008F0C_INDEX_STRIDE(index_stride) |
 			  S_008F0C_ADD_TID_ENABLE(add_tid);
 
+		if (sctx->b.chip_class >= GFX9)
+			assert(!swizzle || element_size == 1); /* always 4 bytes on GFX9 */
+		else
+			desc[3] |= S_008F0C_ELEMENT_SIZE(element_size);
+
 		pipe_resource_reference(&buffers->buffers[slot], buffer);
 		radeon_add_to_buffer_list(&sctx->b, &sctx->b.gfx,
 				      (struct r600_resource*)buffer,
 				      buffers->shader_usage, buffers->priority);
 		buffers->enabled_mask |= 1u << slot;
 	} else {
 		/* Clear the descriptor. */
 		memset(descs->list + slot*4, 0, sizeof(uint32_t) * 4);
 		buffers->enabled_mask &= ~(1u << slot);
 	}
-- 
2.7.4