[Mesa-dev] [PATCH] gallium: remove TGSI_OPCODE_KILL
Ilia Mirkin
imirkin at alum.mit.edu
Thu Oct 5 14:45:56 UTC 2017
Like Roland, I don't see what's being gained. It's more code
everywhere and harder to read the TGSI directly.
Neither nv30 nor nv50+ do the checks you suggest.
On Thu, Oct 5, 2017 at 9:00 AM, Marek Olšák <maraeo at gmail.com> wrote:
> I understand, but you can get KILL by checking if src0 is an immediate. You
> don't even have to check the value, because you are guaranteed it's the
> right one. That makes KILL a strict subset of KILL_IF.
>
> Marek
>
> On Oct 5, 2017 1:08 AM, "Roland Scheidegger" <sroland at vmware.com> wrote:
>
> I didn't like this when it was proposed a couple weeks ago, and
> unsurprisingly I still don't like it now.
> The reason is that KILL is a simple opcode which even maps to what both
> glsl and d3d10 actually need, whereas KILL_IF is a complicated mess
> including combined per-channel comparisons.
> I realize you can of course optimize away all the comparisons if you're
> using immediates, but it still doesn't look very clean to me.
>
> Roland
>
>
> Am 04.10.2017 um 23:15 schrieb Marek Olšák:
>> From: Marek Olšák <marek.olsak at amd.com>
>>
>> It can be recognized from KILL_IF by checking if the src operand is IMM.
>> ---
>> src/gallium/auxiliary/gallivm/lp_bld_tgsi_action.c | 11 ------
>> src/gallium/auxiliary/gallivm/lp_bld_tgsi_aos.c | 3 --
>> src/gallium/auxiliary/gallivm/lp_bld_tgsi_soa.c | 42
>> ----------------------
>> src/gallium/auxiliary/nir/tgsi_to_nir.c | 14 --------
>> src/gallium/auxiliary/tgsi/tgsi_exec.c | 18 ----------
>> src/gallium/auxiliary/tgsi/tgsi_info_opcodes.h | 2 +-
>> src/gallium/auxiliary/tgsi/tgsi_opcode_tmp.h | 1 -
>> src/gallium/auxiliary/tgsi/tgsi_scan.c | 3 +-
>> src/gallium/auxiliary/vl/vl_mc.c | 2 +-
>> src/gallium/docs/source/tgsi.rst | 5 ---
>> src/gallium/drivers/i915/i915_fpc_optimize.c | 1 -
>> src/gallium/drivers/i915/i915_fpc_translate.c | 13 -------
>> .../drivers/nouveau/codegen/nv50_ir_from_tgsi.cpp | 3 --
>> src/gallium/drivers/nouveau/nv30/nvfx_fragprog.c | 3 --
>> src/gallium/drivers/r300/r300_tgsi_to_rc.c | 1 -
>> src/gallium/drivers/r600/r600_shader.c | 13 +++----
>> src/gallium/drivers/radeonsi/si_shader_tgsi_alu.c | 32 ++++++-----------
>> src/gallium/drivers/svga/svga_tgsi_insn.c | 29 +--------------
>> src/gallium/drivers/svga/svga_tgsi_vgpu10.c | 21 -----------
>> src/gallium/include/pipe/p_shader_tokens.h | 2 +-
>> src/mesa/state_tracker/st_glsl_to_tgsi.cpp | 3 +-
>> 21 files changed, 22 insertions(+), 200 deletions(-)
>>
>> diff --git a/src/gallium/auxiliary/gallivm/lp_bld_tgsi_action.c
>> b/src/gallium/auxiliary/gallivm/lp_bld_tgsi_action.c
>> index ce2b927..edcfc6e 100644
>> --- a/src/gallium/auxiliary/gallivm/lp_bld_tgsi_action.c
>> +++ b/src/gallium/auxiliary/gallivm/lp_bld_tgsi_action.c
>> @@ -355,30 +355,20 @@ kil_fetch_args(
>> /* src0.z */
>> emit_data->args[2] = lp_build_emit_fetch(bld_base, emit_data->inst,
>> 0, TGSI_CHAN_Z);
>> /* src0.w */
>> emit_data->args[3] = lp_build_emit_fetch(bld_base, emit_data->inst,
>> 0, TGSI_CHAN_W);
>> emit_data->arg_count = 4;
>> emit_data->dst_type =
>> LLVMVoidTypeInContext(bld_base->base.gallivm->context);
>> }
>>
>> -/* TGSI_OPCODE_KILL */
>> -
>> -static void
>> -kilp_fetch_args(
>> - struct lp_build_tgsi_context * bld_base,
>> - struct lp_build_emit_data * emit_data)
>> -{
>> - emit_data->dst_type =
>> LLVMVoidTypeInContext(bld_base->base.gallivm->context);
>> -}
>> -
>> /* TGSI_OPCODE_LIT */
>>
>> static void
>> lit_fetch_args(
>> struct lp_build_tgsi_context * bld_base,
>> struct lp_build_emit_data * emit_data)
>> {
>> /* src0.x */
>> emit_data->args[0] = lp_build_emit_fetch(bld_base, emit_data->inst, 0,
>> TGSI_CHAN_X);
>> /* src0.y */
>> @@ -1172,21 +1162,20 @@ lp_set_default_actions(struct
>> lp_build_tgsi_context * bld_base)
>> bld_base->op_actions[TGSI_OPCODE_POW] = pow_action;
>> bld_base->op_actions[TGSI_OPCODE_UP2H] = up2h_action;
>>
>> bld_base->op_actions[TGSI_OPCODE_SWITCH].fetch_args =
>> scalar_unary_fetch_args;
>> bld_base->op_actions[TGSI_OPCODE_CASE].fetch_args =
>> scalar_unary_fetch_args;
>> bld_base->op_actions[TGSI_OPCODE_COS].fetch_args =
>> scalar_unary_fetch_args;
>> bld_base->op_actions[TGSI_OPCODE_EX2].fetch_args =
>> scalar_unary_fetch_args;
>> bld_base->op_actions[TGSI_OPCODE_IF].fetch_args =
>> scalar_unary_fetch_args;
>> bld_base->op_actions[TGSI_OPCODE_UIF].fetch_args =
>> scalar_unary_fetch_args;
>> bld_base->op_actions[TGSI_OPCODE_KILL_IF].fetch_args = kil_fetch_args;
>> - bld_base->op_actions[TGSI_OPCODE_KILL].fetch_args = kilp_fetch_args;
>> bld_base->op_actions[TGSI_OPCODE_RCP].fetch_args =
>> scalar_unary_fetch_args;
>> bld_base->op_actions[TGSI_OPCODE_SIN].fetch_args =
>> scalar_unary_fetch_args;
>> bld_base->op_actions[TGSI_OPCODE_LG2].fetch_args =
>> scalar_unary_fetch_args;
>>
>> bld_base->op_actions[TGSI_OPCODE_ADD].emit = add_emit;
>> bld_base->op_actions[TGSI_OPCODE_ARR].emit = arr_emit;
>> bld_base->op_actions[TGSI_OPCODE_END].emit = end_emit;
>> bld_base->op_actions[TGSI_OPCODE_FRC].emit = frc_emit;
>> bld_base->op_actions[TGSI_OPCODE_LRP].emit = lrp_emit;
>> bld_base->op_actions[TGSI_OPCODE_MAD].emit = mad_emit;
>> diff --git a/src/gallium/auxiliary/gallivm/lp_bld_tgsi_aos.c
>> b/src/gallium/auxiliary/gallivm/lp_bld_tgsi_aos.c
>> index 2529c6a..675b9a5 100644
>> --- a/src/gallium/auxiliary/gallivm/lp_bld_tgsi_aos.c
>> +++ b/src/gallium/auxiliary/gallivm/lp_bld_tgsi_aos.c
>> @@ -595,23 +595,20 @@ lp_emit_instruction_aos(
>> tmp0 = swizzle_scalar_aos(bld, src0, TGSI_SWIZZLE_X);
>> dst0 = lp_build_cos(&bld->bld_base.base, tmp0);
>> break;
>>
>> case TGSI_OPCODE_DDX:
>> return FALSE;
>>
>> case TGSI_OPCODE_DDY:
>> return FALSE;
>>
>> - case TGSI_OPCODE_KILL:
>> - return FALSE;
>> -
>> case TGSI_OPCODE_KILL_IF:
>> return FALSE;
>>
>> case TGSI_OPCODE_PK2H:
>> return FALSE;
>> break;
>>
>> case TGSI_OPCODE_PK2US:
>> return FALSE;
>> break;
>> diff --git a/src/gallium/auxiliary/gallivm/lp_bld_tgsi_soa.c
>> b/src/gallium/auxiliary/gallivm/lp_bld_tgsi_soa.c
>> index de18f62..7528b7c 100644
>> --- a/src/gallium/auxiliary/gallivm/lp_bld_tgsi_soa.c
>> +++ b/src/gallium/auxiliary/gallivm/lp_bld_tgsi_soa.c
>> @@ -2705,50 +2705,20 @@ emit_kill_if(
>> mask = LLVMBuildOr(builder, mask, invmask, "");
>> }
>>
>> lp_build_mask_update(bld->mask, mask);
>> if (!near_end_of_shader(bld, pc))
>> lp_build_mask_check(bld->mask);
>> }
>>
>>
>> /**
>> - * Unconditional fragment kill.
>> - * The only predication is the execution mask which will apply if
>> - * we're inside a loop or conditional.
>> - */
>> -static void
>> -emit_kill(struct lp_build_tgsi_soa_context *bld,
>> - int pc)
>> -{
>> - LLVMBuilderRef builder = bld->bld_base.base.gallivm->builder;
>> - LLVMValueRef mask;
>> -
>> - /* For those channels which are "alive", disable fragment shader
>> - * execution.
>> - */
>> - if (bld->exec_mask.has_mask) {
>> - mask = LLVMBuildNot(builder, bld->exec_mask.exec_mask, "kilp");
>> - }
>> - else {
>> - LLVMValueRef zero = LLVMConstNull(bld->bld_base.base.int_vec_type);
>> - mask = zero;
>> - }
>> -
>> - lp_build_mask_update(bld->mask, mask);
>> -
>> - if (!near_end_of_shader(bld, pc))
>> - lp_build_mask_check(bld->mask);
>> -}
>> -
>> -
>> -/**
>> * Emit code which will dump the value of all the temporary registers
>> * to stdout.
>> */
>> static void
>> emit_dump_file(struct lp_build_tgsi_soa_context *bld,
>> unsigned file)
>> {
>> const struct tgsi_shader_info *info = bld->bld_base.info;
>> struct gallivm_state *gallivm = bld->bld_base.base.gallivm;
>> LLVMBuilderRef builder = gallivm->builder;
>> @@ -3008,31 +2978,20 @@ ddy_emit(
>> struct lp_build_tgsi_context * bld_base,
>> struct lp_build_emit_data * emit_data)
>> {
>> struct lp_build_tgsi_soa_context * bld = lp_soa_context(bld_base);
>>
>> emit_fetch_deriv(bld, emit_data->args[0], NULL, NULL,
>> &emit_data->output[emit_data->chan]);
>> }
>>
>> static void
>> -kill_emit(
>> - const struct lp_build_tgsi_action * action,
>> - struct lp_build_tgsi_context * bld_base,
>> - struct lp_build_emit_data * emit_data)
>> -{
>> - struct lp_build_tgsi_soa_context * bld = lp_soa_context(bld_base);
>> -
>> - emit_kill(bld, bld_base->pc - 1);
>> -}
>> -
>> -static void
>> kill_if_emit(
>> const struct lp_build_tgsi_action * action,
>> struct lp_build_tgsi_context * bld_base,
>> struct lp_build_emit_data * emit_data)
>> {
>> struct lp_build_tgsi_soa_context * bld = lp_soa_context(bld_base);
>>
>> emit_kill_if(bld, emit_data->inst, bld_base->pc - 1);
>> }
>>
>> @@ -3877,21 +3836,20 @@ lp_build_tgsi_soa(struct gallivm_state *gallivm,
>> bld.bld_base.op_actions[TGSI_OPCODE_DDY].emit = ddy_emit;
>> bld.bld_base.op_actions[TGSI_OPCODE_DEFAULT].emit = default_emit;
>> bld.bld_base.op_actions[TGSI_OPCODE_ELSE].emit = else_emit;
>> bld.bld_base.op_actions[TGSI_OPCODE_ENDIF].emit = endif_emit;
>> bld.bld_base.op_actions[TGSI_OPCODE_ENDLOOP].emit = endloop_emit;
>> bld.bld_base.op_actions[TGSI_OPCODE_ENDSUB].emit = endsub_emit;
>> bld.bld_base.op_actions[TGSI_OPCODE_ENDSWITCH].emit = endswitch_emit;
>> bld.bld_base.op_actions[TGSI_OPCODE_IF].emit = if_emit;
>> bld.bld_base.op_actions[TGSI_OPCODE_UIF].emit = uif_emit;
>> bld.bld_base.op_actions[TGSI_OPCODE_KILL_IF].emit = kill_if_emit;
>> - bld.bld_base.op_actions[TGSI_OPCODE_KILL].emit = kill_emit;
>> bld.bld_base.op_actions[TGSI_OPCODE_RET].emit = ret_emit;
>> bld.bld_base.op_actions[TGSI_OPCODE_SWITCH].emit = switch_emit;
>> bld.bld_base.op_actions[TGSI_OPCODE_TEX].emit = tex_emit;
>> bld.bld_base.op_actions[TGSI_OPCODE_TXB].emit = txb_emit;
>> bld.bld_base.op_actions[TGSI_OPCODE_TXD].emit = txd_emit;
>> bld.bld_base.op_actions[TGSI_OPCODE_TXL].emit = txl_emit;
>> bld.bld_base.op_actions[TGSI_OPCODE_TXP].emit = txp_emit;
>> bld.bld_base.op_actions[TGSI_OPCODE_TXQ].emit = txq_emit;
>> bld.bld_base.op_actions[TGSI_OPCODE_TXF].emit = txf_emit;
>> bld.bld_base.op_actions[TGSI_OPCODE_TEX2].emit = tex2_emit;
>> diff --git a/src/gallium/auxiliary/nir/tgsi_to_nir.c
>> b/src/gallium/auxiliary/nir/tgsi_to_nir.c
>> index a317552..04658e3 100644
>> --- a/src/gallium/auxiliary/nir/tgsi_to_nir.c
>> +++ b/src/gallium/auxiliary/nir/tgsi_to_nir.c
>> @@ -1010,29 +1010,20 @@ ttn_cmp(nir_builder *b, nir_op op, nir_alu_dest
>> dest, nir_ssa_def **src)
>>
>> static void
>> ttn_ucmp(nir_builder *b, nir_op op, nir_alu_dest dest, nir_ssa_def **src)
>> {
>> ttn_move_dest(b, dest, nir_bcsel(b,
>> nir_ine(b, src[0], nir_imm_int(b,
>> 0)),
>> src[1], src[2]));
>> }
>>
>> static void
>> -ttn_kill(nir_builder *b, nir_op op, nir_alu_dest dest, nir_ssa_def **src)
>> -{
>> - nir_intrinsic_instr *discard =
>> - nir_intrinsic_instr_create(b->shader, nir_intrinsic_discard);
>> - nir_builder_instr_insert(b, &discard->instr);
>> - b->shader->info.fs.uses_discard = true;
>> -}
>> -
>> -static void
>> ttn_kill_if(nir_builder *b, nir_op op, nir_alu_dest dest, nir_ssa_def
>> **src)
>> {
>> nir_ssa_def *cmp = nir_bany_inequal4(b, nir_flt(b, src[0],
>> nir_imm_float(b,
>> 0.0)),
>> nir_imm_int(b, 0));
>> nir_intrinsic_instr *discard =
>> nir_intrinsic_instr_create(b->shader, nir_intrinsic_discard_if);
>> discard->src[0] = nir_src_for_ssa(cmp);
>> nir_builder_instr_insert(b, &discard->instr);
>> b->shader->info.fs.uses_discard = true;
>> @@ -1492,21 +1483,20 @@ static const nir_op op_trans[TGSI_OPCODE_LAST] = {
>> [TGSI_OPCODE_SQRT] = nir_op_fsqrt,
>> [TGSI_OPCODE_FRC] = nir_op_ffract,
>> [TGSI_OPCODE_FLR] = nir_op_ffloor,
>> [TGSI_OPCODE_ROUND] = nir_op_fround_even,
>> [TGSI_OPCODE_EX2] = nir_op_fexp2,
>> [TGSI_OPCODE_LG2] = nir_op_flog2,
>> [TGSI_OPCODE_POW] = nir_op_fpow,
>> [TGSI_OPCODE_COS] = nir_op_fcos,
>> [TGSI_OPCODE_DDX] = nir_op_fddx,
>> [TGSI_OPCODE_DDY] = nir_op_fddy,
>> - [TGSI_OPCODE_KILL] = 0,
>> [TGSI_OPCODE_PK2H] = 0, /* XXX */
>> [TGSI_OPCODE_PK2US] = 0, /* XXX */
>> [TGSI_OPCODE_PK4B] = 0, /* XXX */
>> [TGSI_OPCODE_PK4UB] = 0, /* XXX */
>> [TGSI_OPCODE_SEQ] = nir_op_seq,
>> [TGSI_OPCODE_SGT] = 0,
>> [TGSI_OPCODE_SIN] = nir_op_fsin,
>> [TGSI_OPCODE_SNE] = nir_op_sne,
>> [TGSI_OPCODE_SLE] = 0,
>> [TGSI_OPCODE_TEX] = 0,
>> @@ -1717,24 +1707,20 @@ ttn_emit_instruction(struct ttn_compile *c)
>> break;
>>
>> case TGSI_OPCODE_UMAD:
>> ttn_umad(b, op_trans[tgsi_op], dest, src);
>> break;
>>
>> case TGSI_OPCODE_LRP:
>> ttn_move_dest(b, dest, nir_flrp(b, src[2], src[1], src[0]));
>> break;
>>
>> - case TGSI_OPCODE_KILL:
>> - ttn_kill(b, op_trans[tgsi_op], dest, src);
>> - break;
>> -
>> case TGSI_OPCODE_ARR:
>> ttn_arr(b, op_trans[tgsi_op], dest, src);
>> break;
>>
>> case TGSI_OPCODE_CMP:
>> ttn_cmp(b, op_trans[tgsi_op], dest, src);
>> break;
>>
>> case TGSI_OPCODE_UCMP:
>> ttn_ucmp(b, op_trans[tgsi_op], dest, src);
>> diff --git a/src/gallium/auxiliary/tgsi/tgsi_exec.c
>> b/src/gallium/auxiliary/tgsi/tgsi_exec.c
>> index afed96c..87c3146 100644
>> --- a/src/gallium/auxiliary/tgsi/tgsi_exec.c
>> +++ b/src/gallium/auxiliary/tgsi/tgsi_exec.c
>> @@ -2034,34 +2034,20 @@ exec_kill_if(struct tgsi_exec_machine *mach,
>> if (r[0].f[i] < 0.0f)
>> kilmask |= 1 << i;
>> }
>>
>> /* restrict to fragments currently executing */
>> kilmask &= mach->ExecMask;
>>
>> mach->Temps[TEMP_KILMASK_I].xyzw[TEMP_KILMASK_C].u[0] |= kilmask;
>> }
>>
>> -/**
>> - * Unconditional fragment kill/discard.
>> - */
>> -static void
>> -exec_kill(struct tgsi_exec_machine *mach,
>> - const struct tgsi_full_instruction *inst)
>> -{
>> - uint kilmask; /* bit 0 = pixel 0, bit 1 = pixel 1, etc */
>> -
>> - /* kill fragment for all fragments currently executing */
>> - kilmask = mach->ExecMask;
>> - mach->Temps[TEMP_KILMASK_I].xyzw[TEMP_KILMASK_C].u[0] |= kilmask;
>> -}
>> -
>> static void
>> emit_vertex(struct tgsi_exec_machine *mach)
>> {
>> /* FIXME: check for exec mask correctly
>> unsigned i;
>> for (i = 0; i < TGSI_QUAD_SIZE; ++i) {
>> if ((mach->ExecMask & (1 << i)))
>> */
>> if (mach->ExecMask) {
>> if
>> (mach->Primitives[mach->Temps[TEMP_PRIMITIVE_I].xyzw[TEMP_PRIMITIVE_C].u[0]]
>> >= mach->MaxOutputVertices)
>> @@ -5138,24 +5124,20 @@ exec_instruction(
>> break;
>>
>> case TGSI_OPCODE_DDX:
>> exec_vector_unary(mach, inst, micro_ddx, TGSI_EXEC_DATA_FLOAT,
>> TGSI_EXEC_DATA_FLOAT);
>> break;
>>
>> case TGSI_OPCODE_DDY:
>> exec_vector_unary(mach, inst, micro_ddy, TGSI_EXEC_DATA_FLOAT,
>> TGSI_EXEC_DATA_FLOAT);
>> break;
>>
>> - case TGSI_OPCODE_KILL:
>> - exec_kill (mach, inst);
>> - break;
>> -
>> case TGSI_OPCODE_KILL_IF:
>> exec_kill_if (mach, inst);
>> break;
>>
>> case TGSI_OPCODE_PK2H:
>> exec_pk2h(mach, inst);
>> break;
>>
>> case TGSI_OPCODE_PK2US:
>> assert (0);
>> diff --git a/src/gallium/auxiliary/tgsi/tgsi_info_opcodes.h
>> b/src/gallium/auxiliary/tgsi/tgsi_info_opcodes.h
>> index 1b2803c..61dfbd5 100644
>> --- a/src/gallium/auxiliary/tgsi/tgsi_info_opcodes.h
>> +++ b/src/gallium/auxiliary/tgsi/tgsi_info_opcodes.h
>> @@ -30,21 +30,21 @@ OPCODE(1, 1, REPL, EX2)
>> OPCODE(1, 1, REPL, LG2)
>> OPCODE(1, 2, REPL, POW)
>> OPCODE_GAP(31) /* removed */
>> OPCODE(1, 1, COMP, U2I64)
>> OPCODE(1, 0, OTHR, CLOCK)
>> OPCODE(1, 1, COMP, I2I64)
>> OPCODE_GAP(35) /* removed */
>> OPCODE(1, 1, REPL, COS)
>> OPCODE(1, 1, COMP, DDX)
>> OPCODE(1, 1, COMP, DDY)
>> -OPCODE(0, 0, NONE, KILL)
>> +OPCODE_GAP(39) /* removed */
>> OPCODE(1, 1, REPL, PK2H)
>> OPCODE(1, 1, REPL, PK2US)
>> OPCODE(1, 1, REPL, PK4B)
>> OPCODE(1, 1, REPL, PK4UB)
>> OPCODE(1, 1, COMP, D2U64)
>> OPCODE(1, 2, COMP, SEQ)
>> OPCODE(1, 1, COMP, D2I64)
>> OPCODE(1, 2, COMP, SGT)
>> OPCODE(1, 1, REPL, SIN)
>> OPCODE(1, 2, COMP, SLE)
>> diff --git a/src/gallium/auxiliary/tgsi/tgsi_opcode_tmp.h
>> b/src/gallium/auxiliary/tgsi/tgsi_opcode_tmp.h
>> index 9a13fa6..809ce77 100644
>> --- a/src/gallium/auxiliary/tgsi/tgsi_opcode_tmp.h
>> +++ b/src/gallium/auxiliary/tgsi/tgsi_opcode_tmp.h
>> @@ -61,21 +61,20 @@ OP12_TEX(TXF_LZ)
>> OP11(FLR)
>> OP11(ROUND)
>> OP11(EX2)
>> OP11(LG2)
>> OP12(POW)
>> OP11(COS)
>> OP11(DDX)
>> OP11(DDY)
>> OP11(DDX_FINE)
>> OP11(DDY_FINE)
>> -OP00(KILL)
>> OP11(PK2H)
>> OP11(PK2US)
>> OP11(PK4B)
>> OP11(PK4UB)
>> OP12(SEQ)
>> OP12(SGT)
>> OP11(SIN)
>> OP12(SLE)
>> OP12(SNE)
>> OP12_TEX(TEX)
>> diff --git a/src/gallium/auxiliary/tgsi/tgsi_scan.c
>> b/src/gallium/auxiliary/tgsi/tgsi_scan.c
>> index 989c57e..dceb8e2 100644
>> --- a/src/gallium/auxiliary/tgsi/tgsi_scan.c
>> +++ b/src/gallium/auxiliary/tgsi/tgsi_scan.c
>> @@ -860,22 +860,21 @@ tgsi_scan_shader(const struct tgsi_token *tokens,
>> scan_immediate(info);
>> break;
>> case TGSI_TOKEN_TYPE_PROPERTY:
>> scan_property(info, &parse.FullToken.FullProperty);
>> break;
>> default:
>> assert(!"Unexpected TGSI token type");
>> }
>> }
>>
>> - info->uses_kill = (info->opcode_count[TGSI_OPCODE_KILL_IF] ||
>> - info->opcode_count[TGSI_OPCODE_KILL]);
>> + info->uses_kill = info->opcode_count[TGSI_OPCODE_KILL_IF] > 0;
>>
>> /* The dimensions of the IN decleration in geometry shader have
>> * to be deduced from the type of the input primitive.
>> */
>> if (procType == PIPE_SHADER_GEOMETRY) {
>> unsigned input_primitive =
>> info->properties[TGSI_PROPERTY_GS_INPUT_PRIM];
>> int num_verts = u_vertices_per_prim(input_primitive);
>> int j;
>> info->file_count[TGSI_FILE_INPUT] = num_verts;
>> diff --git a/src/gallium/auxiliary/vl/vl_mc.c
>> b/src/gallium/auxiliary/vl/vl_mc.c
>> index a202fac..583539e 100644
>> --- a/src/gallium/auxiliary/vl/vl_mc.c
>> +++ b/src/gallium/auxiliary/vl/vl_mc.c
>> @@ -337,21 +337,21 @@ create_ycbcr_frag_shader(struct vl_mc *r, float
>> scale, bool invert,
>> * fragment.xyz = tex(tc, sampler) * scale + tc.z
>> * fragment.w = 1.0f
>> * }
>> */
>>
>> ureg_SEQ(shader, ureg_writemask(tmp, TGSI_WRITEMASK_Y),
>> ureg_scalar(flags, TGSI_SWIZZLE_W), ureg_src(tmp));
>>
>> ureg_IF(shader, ureg_scalar(ureg_src(tmp), TGSI_SWIZZLE_Y), &label);
>>
>> - ureg_KILL(shader);
>> + ureg_KILL_IF(shader, ureg_imm1f(shader, -1.0));
>>
>> ureg_fixup_label(shader, label, ureg_get_instruction_number(shader));
>> ureg_ELSE(shader, &label);
>>
>> fs_callback(callback_priv, r, shader, VS_O_VTEX, tmp);
>>
>> if (scale != 1.0f)
>> ureg_MAD(shader, ureg_writemask(tmp, TGSI_WRITEMASK_XYZ),
>> ureg_src(tmp), ureg_imm1f(shader, scale),
>> ureg_scalar(flags, TGSI_SWIZZLE_Z));
>> diff --git a/src/gallium/docs/source/tgsi.rst
>> b/src/gallium/docs/source/tgsi.rst
>> index 1a51fe9..93cc57c 100644
>> --- a/src/gallium/docs/source/tgsi.rst
>> +++ b/src/gallium/docs/source/tgsi.rst
>> @@ -669,25 +669,20 @@ This instruction replicates its result.
>>
>> Conditional discard. Allowed in fragment shaders only.
>>
>> .. math::
>>
>> if (src.x < 0 || src.y < 0 || src.z < 0 || src.w < 0)
>> discard
>> endif
>>
>>
>> -.. opcode:: KILL - Discard
>> -
>> - Unconditional discard. Allowed in fragment shaders only.
>> -
>> -
>> .. opcode:: TXB - Texture Lookup With Bias
>>
>> for cube map array textures and shadow cube maps, the bias value
>> cannot be passed in src0.w, and TXB2 must be used instead.
>>
>> if the target is a shadow texture, the reference value is always
>> in src.z (this prevents shadow 3d and shadow 2d arrays from
>> using this instruction, but this is not needed).
>>
>> .. math::
>> diff --git a/src/gallium/drivers/i915/i915_fpc_optimize.c
>> b/src/gallium/drivers/i915/i915_fpc_optimize.c
>> index 76ef20d..5b53179 100644
>> --- a/src/gallium/drivers/i915/i915_fpc_optimize.c
>> +++ b/src/gallium/drivers/i915/i915_fpc_optimize.c
>> @@ -84,21 +84,20 @@ static const struct {
>> [ TGSI_OPCODE_DDY ] = { false, false, 0, 1, 0
>> },
>> [ TGSI_OPCODE_DP2 ] = { false, true, TGSI_SWIZZLE_ONE, 1, 2
>> },
>> [ TGSI_OPCODE_DP3 ] = { false, true, TGSI_SWIZZLE_ONE, 1, 2
>> },
>> [ TGSI_OPCODE_DP4 ] = { false, true, TGSI_SWIZZLE_ONE, 1, 2
>> },
>> [ TGSI_OPCODE_DST ] = { false, false, 0, 1, 2
>> },
>> [ TGSI_OPCODE_END ] = { false, false, 0, 0, 0
>> },
>> [ TGSI_OPCODE_EX2 ] = { false, false, 0, 1, 1
>> },
>> [ TGSI_OPCODE_FLR ] = { false, false, 0, 1, 1
>> },
>> [ TGSI_OPCODE_FRC ] = { false, false, 0, 1, 1
>> },
>> [ TGSI_OPCODE_KILL_IF ] = { false, false, 0, 0, 1
>> },
>> - [ TGSI_OPCODE_KILL ] = { false, false, 0, 0, 0
>> },
>> [ TGSI_OPCODE_LG2 ] = { false, false, 0, 1, 1
>> },
>> [ TGSI_OPCODE_LIT ] = { false, false, 0, 1, 1
>> },
>> [ TGSI_OPCODE_LRP ] = { false, false, 0, 1, 3
>> },
>> [ TGSI_OPCODE_MAX ] = { false, false, 0, 1, 2
>> },
>> [ TGSI_OPCODE_MAD ] = { false, false, 0, 1, 3
>> },
>> [ TGSI_OPCODE_MIN ] = { false, false, 0, 1, 2
>> },
>> [ TGSI_OPCODE_MOV ] = { false, false, 0, 1, 1
>> },
>> [ TGSI_OPCODE_MUL ] = { false, true, TGSI_SWIZZLE_ONE, 1, 2
>> },
>> [ TGSI_OPCODE_NOP ] = { false, false, 0, 0, 0
>> },
>> [ TGSI_OPCODE_POW ] = { false, false, 0, 1, 2
>> },
>> diff --git a/src/gallium/drivers/i915/i915_fpc_translate.c
>> b/src/gallium/drivers/i915/i915_fpc_translate.c
>> index 2eaa1e6..054d08d 100644
>> --- a/src/gallium/drivers/i915/i915_fpc_translate.c
>> +++ b/src/gallium/drivers/i915/i915_fpc_translate.c
>> @@ -634,33 +634,20 @@ i915_translate_instruction(struct i915_fp_compile
>> *p,
>>
>> i915_emit_texld(p,
>> tmp, /* dest reg: a dummy reg */
>> A0_DEST_CHANNEL_ALL, /* dest writemask */
>> 0, /* sampler */
>> src0, /* coord*/
>> T0_TEXKILL, /* opcode */
>> 1); /* num_coord */
>> break;
>>
>> - case TGSI_OPCODE_KILL:
>> - /* unconditional kill */
>> - tmp = i915_get_utemp(p);
>> -
>> - i915_emit_texld(p,
>> - tmp, /* dest reg:
>> a dummy reg */
>> - A0_DEST_CHANNEL_ALL, /* dest
>> writemask */
>> - 0, /* sampler
>> */
>> - negate(swizzle(0, ONE, ONE, ONE, ONE), 1, 1, 1, 1),
>> /* coord */
>> - T0_TEXKILL, /* opcode */
>> - 1); /* num_coord
>> */
>> - break;
>> -
>> case TGSI_OPCODE_LG2:
>> src0 = src_vector(p, &inst->Src[0], fs);
>>
>> i915_emit_arith(p,
>> A0_LOG,
>> get_result_vector(p, &inst->Dst[0]),
>> get_result_flags(inst), 0,
>> swizzle(src0, X, X, X, X), 0, 0);
>> break;
>>
>> diff --git a/src/gallium/drivers/nouveau/codegen/nv50_ir_from_tgsi.cpp
>> b/src/gallium/drivers/nouveau/codegen/nv50_ir_from_tgsi.cpp
>> index 2780605..34c4c3a 100644
>> --- a/src/gallium/drivers/nouveau/codegen/nv50_ir_from_tgsi.cpp
>> +++ b/src/gallium/drivers/nouveau/codegen/nv50_ir_from_tgsi.cpp
>> @@ -3439,23 +3439,20 @@ Converter::handleInstruction(const struct
>> tgsi_full_instruction *insn)
>> mask = 0;
>> for (c = 0; c < 4; ++c) {
>> const int s = tgsi.getSrc(0).getSwizzle(c);
>> if (mask & (1 << s))
>> continue;
>> mask |= 1 << s;
>> mkCmp(OP_SET, CC_LT, TYPE_F32, val0, TYPE_F32, fetchSrc(0, c),
>> zero);
>> mkOp(OP_DISCARD, TYPE_NONE, NULL)->setPredicate(CC_P, val0);
>> }
>> break;
>> - case TGSI_OPCODE_KILL:
>> - mkOp(OP_DISCARD, TYPE_NONE, NULL);
>> - break;
>> case TGSI_OPCODE_TEX:
>> case TGSI_OPCODE_TEX_LZ:
>> case TGSI_OPCODE_TXB:
>> case TGSI_OPCODE_TXL:
>> case TGSI_OPCODE_TXP:
>> case TGSI_OPCODE_LODQ:
>> // R S L C Dx Dy
>> handleTEX(dst0, 1, 1, 0x03, 0x0f, 0x00, 0x00);
>> break;
>> case TGSI_OPCODE_TXD:
>> diff --git a/src/gallium/drivers/nouveau/nv30/nvfx_fragprog.c
>> b/src/gallium/drivers/nouveau/nv30/nvfx_fragprog.c
>> index 86e3599..623ceed 100644
>> --- a/src/gallium/drivers/nouveau/nv30/nvfx_fragprog.c
>> +++ b/src/gallium/drivers/nouveau/nv30/nvfx_fragprog.c
>> @@ -596,23 +596,20 @@ nvfx_fragprog_parse_instruction(struct nvfx_fpc
>> *fpc,
>> break;
>> case TGSI_OPCODE_EX2:
>> nvfx_fp_emit(fpc, arith(sat, EX2, dst, mask, src[0], none, none));
>> break;
>> case TGSI_OPCODE_FLR:
>> nvfx_fp_emit(fpc, arith(sat, FLR, dst, mask, src[0], none, none));
>> break;
>> case TGSI_OPCODE_FRC:
>> nvfx_fp_emit(fpc, arith(sat, FRC, dst, mask, src[0], none, none));
>> break;
>> - case TGSI_OPCODE_KILL:
>> - nvfx_fp_emit(fpc, arith(0, KIL, none.reg, 0, none, none, none));
>> - break;
>> case TGSI_OPCODE_KILL_IF:
>> insn = arith(0, MOV, none.reg, NVFX_FP_MASK_ALL, src[0], none,
>> none);
>> insn.cc_update = 1;
>> nvfx_fp_emit(fpc, insn);
>>
>> insn = arith(0, KIL, none.reg, 0, none, none, none);
>> insn.cc_test = NVFX_COND_LT;
>> nvfx_fp_emit(fpc, insn);
>> break;
>> case TGSI_OPCODE_LG2:
>> diff --git a/src/gallium/drivers/r300/r300_tgsi_to_rc.c
>> b/src/gallium/drivers/r300/r300_tgsi_to_rc.c
>> index 3030698..a660cec 100644
>> --- a/src/gallium/drivers/r300/r300_tgsi_to_rc.c
>> +++ b/src/gallium/drivers/r300/r300_tgsi_to_rc.c
>> @@ -53,21 +53,20 @@ static unsigned translate_opcode(unsigned opcode)
>> case TGSI_OPCODE_LRP: return RC_OPCODE_LRP;
>> case TGSI_OPCODE_FRC: return RC_OPCODE_FRC;
>> case TGSI_OPCODE_FLR: return RC_OPCODE_FLR;
>> case TGSI_OPCODE_ROUND: return RC_OPCODE_ROUND;
>> case TGSI_OPCODE_EX2: return RC_OPCODE_EX2;
>> case TGSI_OPCODE_LG2: return RC_OPCODE_LG2;
>> case TGSI_OPCODE_POW: return RC_OPCODE_POW;
>> case TGSI_OPCODE_COS: return RC_OPCODE_COS;
>> case TGSI_OPCODE_DDX: return RC_OPCODE_DDX;
>> case TGSI_OPCODE_DDY: return RC_OPCODE_DDY;
>> - case TGSI_OPCODE_KILL: return RC_OPCODE_KILP;
>> /* case TGSI_OPCODE_PK2H: return RC_OPCODE_PK2H; */
>> /* case TGSI_OPCODE_PK2US: return RC_OPCODE_PK2US; */
>> /* case TGSI_OPCODE_PK4B: return RC_OPCODE_PK4B; */
>> /* case TGSI_OPCODE_PK4UB: return RC_OPCODE_PK4UB; */
>> case TGSI_OPCODE_SEQ: return RC_OPCODE_SEQ;
>> case TGSI_OPCODE_SGT: return RC_OPCODE_SGT;
>> case TGSI_OPCODE_SIN: return RC_OPCODE_SIN;
>> case TGSI_OPCODE_SLE: return RC_OPCODE_SLE;
>> case TGSI_OPCODE_SNE: return RC_OPCODE_SNE;
>> case TGSI_OPCODE_TEX: return RC_OPCODE_TEX;
>> diff --git a/src/gallium/drivers/r600/r600_shader.c
>> b/src/gallium/drivers/r600/r600_shader.c
>> index 188fbc9..c879d02 100644
>> --- a/src/gallium/drivers/r600/r600_shader.c
>> +++ b/src/gallium/drivers/r600/r600_shader.c
>> @@ -4611,26 +4611,21 @@ static int tgsi_kill(struct r600_shader_ctx *ctx)
>> int i, r;
>>
>> for (i = 0; i < 4; i++) {
>> memset(&alu, 0, sizeof(struct r600_bytecode_alu));
>> alu.op = ctx->inst_info->op;
>>
>> alu.dst.chan = i;
>>
>> alu.src[0].sel = V_SQ_ALU_SRC_0;
>>
>> - if (inst->Instruction.Opcode == TGSI_OPCODE_KILL) {
>> - alu.src[1].sel = V_SQ_ALU_SRC_1;
>> - alu.src[1].neg = 1;
>> - } else {
>> - r600_bytecode_src(&alu.src[1], &ctx->src[0], i);
>> - }
>> + r600_bytecode_src(&alu.src[1], &ctx->src[0], i);
>> if (i == 3) {
>> alu.last = 1;
>> }
>> r = r600_bytecode_add_alu(ctx->bc, &alu);
>> if (r)
>> return r;
>> }
>>
>> /* kill must be last in ALU */
>> ctx->bc->force_add_cf = 1;
>> @@ -8863,21 +8858,21 @@ static const struct r600_shader_tgsi_instruction
>> r600_shader_tgsi_instruction[]
>> [TGSI_OPCODE_LG2] = { ALU_OP1_LOG_IEEE,
>> tgsi_trans_srcx_replicate},
>> [TGSI_OPCODE_POW] = { ALU_OP0_NOP, tgsi_pow},
>> [31] = { ALU_OP0_NOP, tgsi_unsupported},
>> [32] = { ALU_OP0_NOP, tgsi_unsupported},
>> [33] = { ALU_OP0_NOP, tgsi_unsupported},
>> [34] = { ALU_OP0_NOP, tgsi_unsupported},
>> [35] = { ALU_OP0_NOP, tgsi_unsupported},
>> [TGSI_OPCODE_COS] = { ALU_OP1_COS, tgsi_trig},
>> [TGSI_OPCODE_DDX] = { FETCH_OP_GET_GRADIENTS_H, tgsi_tex},
>> [TGSI_OPCODE_DDY] = { FETCH_OP_GET_GRADIENTS_V, tgsi_tex},
>> - [TGSI_OPCODE_KILL] = { ALU_OP2_KILLGT, tgsi_kill}, /*
>> unconditional kill */
>> + [39] = { ALU_OP0_NOP, tgsi_unsupported},
>> [TGSI_OPCODE_PK2H] = { ALU_OP0_NOP, tgsi_unsupported},
>> [TGSI_OPCODE_PK2US] = { ALU_OP0_NOP, tgsi_unsupported},
>> [TGSI_OPCODE_PK4B] = { ALU_OP0_NOP, tgsi_unsupported},
>> [TGSI_OPCODE_PK4UB] = { ALU_OP0_NOP, tgsi_unsupported},
>> [44] = { ALU_OP0_NOP, tgsi_unsupported},
>> [TGSI_OPCODE_SEQ] = { ALU_OP2_SETE, tgsi_op2},
>> [46] = { ALU_OP0_NOP, tgsi_unsupported},
>> [TGSI_OPCODE_SGT] = { ALU_OP2_SETGT, tgsi_op2},
>> [TGSI_OPCODE_SIN] = { ALU_OP1_SIN, tgsi_trig},
>> [TGSI_OPCODE_SLE] = { ALU_OP2_SETGE, tgsi_op2_swap},
>> @@ -9061,21 +9056,21 @@ static const struct r600_shader_tgsi_instruction
>> eg_shader_tgsi_instruction[] =
>> [TGSI_OPCODE_LG2] = { ALU_OP1_LOG_IEEE,
>> tgsi_trans_srcx_replicate},
>> [TGSI_OPCODE_POW] = { ALU_OP0_NOP, tgsi_pow},
>> [31] = { ALU_OP0_NOP, tgsi_unsupported},
>> [32] = { ALU_OP0_NOP, tgsi_unsupported},
>> [33] = { ALU_OP0_NOP, tgsi_unsupported},
>> [34] = { ALU_OP0_NOP, tgsi_unsupported},
>> [35] = { ALU_OP0_NOP, tgsi_unsupported},
>> [TGSI_OPCODE_COS] = { ALU_OP1_COS, tgsi_trig},
>> [TGSI_OPCODE_DDX] = { FETCH_OP_GET_GRADIENTS_H, tgsi_tex},
>> [TGSI_OPCODE_DDY] = { FETCH_OP_GET_GRADIENTS_V, tgsi_tex},
>> - [TGSI_OPCODE_KILL] = { ALU_OP2_KILLGT, tgsi_kill}, /*
>> unconditional kill */
>> + [39] = { ALU_OP0_NOP, tgsi_unsupported},
>> [TGSI_OPCODE_PK2H] = { ALU_OP0_NOP, tgsi_pk2h},
>> [TGSI_OPCODE_PK2US] = { ALU_OP0_NOP, tgsi_unsupported},
>> [TGSI_OPCODE_PK4B] = { ALU_OP0_NOP, tgsi_unsupported},
>> [TGSI_OPCODE_PK4UB] = { ALU_OP0_NOP, tgsi_unsupported},
>> [44] = { ALU_OP0_NOP, tgsi_unsupported},
>> [TGSI_OPCODE_SEQ] = { ALU_OP2_SETE, tgsi_op2},
>> [46] = { ALU_OP0_NOP, tgsi_unsupported},
>> [TGSI_OPCODE_SGT] = { ALU_OP2_SETGT, tgsi_op2},
>> [TGSI_OPCODE_SIN] = { ALU_OP1_SIN, tgsi_trig},
>> [TGSI_OPCODE_SLE] = { ALU_OP2_SETGE, tgsi_op2_swap},
>> @@ -9284,21 +9279,21 @@ static const struct r600_shader_tgsi_instruction
>> cm_shader_tgsi_instruction[] =
>> [TGSI_OPCODE_LG2] = { ALU_OP1_LOG_IEEE,
>> cayman_emit_float_instr},
>> [TGSI_OPCODE_POW] = { ALU_OP0_NOP, cayman_pow},
>> [31] = { ALU_OP0_NOP, tgsi_unsupported},
>> [32] = { ALU_OP0_NOP, tgsi_unsupported},
>> [33] = { ALU_OP0_NOP, tgsi_unsupported},
>> [34] = { ALU_OP0_NOP, tgsi_unsupported},
>> [35] = { ALU_OP0_NOP, tgsi_unsupported},
>> [TGSI_OPCODE_COS] = { ALU_OP1_COS, cayman_trig},
>> [TGSI_OPCODE_DDX] = { FETCH_OP_GET_GRADIENTS_H, tgsi_tex},
>> [TGSI_OPCODE_DDY] = { FETCH_OP_GET_GRADIENTS_V, tgsi_tex},
>> - [TGSI_OPCODE_KILL] = { ALU_OP2_KILLGT, tgsi_kill}, /*
>> unconditional kill */
>> + [39] = { ALU_OP0_NOP, tgsi_unsupported},
>> [TGSI_OPCODE_PK2H] = { ALU_OP0_NOP, tgsi_pk2h},
>> [TGSI_OPCODE_PK2US] = { ALU_OP0_NOP, tgsi_unsupported},
>> [TGSI_OPCODE_PK4B] = { ALU_OP0_NOP, tgsi_unsupported},
>> [TGSI_OPCODE_PK4UB] = { ALU_OP0_NOP, tgsi_unsupported},
>> [44] = { ALU_OP0_NOP, tgsi_unsupported},
>> [TGSI_OPCODE_SEQ] = { ALU_OP2_SETE, tgsi_op2},
>> [46] = { ALU_OP0_NOP, tgsi_unsupported},
>> [TGSI_OPCODE_SGT] = { ALU_OP2_SETGT, tgsi_op2},
>> [TGSI_OPCODE_SIN] = { ALU_OP1_SIN, cayman_trig},
>> [TGSI_OPCODE_SLE] = { ALU_OP2_SETGE, tgsi_op2_swap},
>> diff --git a/src/gallium/drivers/radeonsi/si_shader_tgsi_alu.c
>> b/src/gallium/drivers/radeonsi/si_shader_tgsi_alu.c
>> index fc705c3..a628837 100644
>> --- a/src/gallium/drivers/radeonsi/si_shader_tgsi_alu.c
>> +++ b/src/gallium/drivers/radeonsi/si_shader_tgsi_alu.c
>> @@ -56,43 +56,34 @@ static void kill_if_fetch_args(struct
>> lp_build_tgsi_context *bld_base,
>> }
>>
>> static void kil_emit(const struct lp_build_tgsi_action *action,
>> struct lp_build_tgsi_context *bld_base,
>> struct lp_build_emit_data *emit_data)
>> {
>> struct si_shader_context *ctx = si_shader_context(bld_base);
>> LLVMBuilderRef builder = ctx->ac.builder;
>>
>> if (ctx->postponed_kill) {
>> - if (emit_data->inst->Instruction.Opcode ==
>> TGSI_OPCODE_KILL_IF) {
>> - LLVMValueRef val;
>> -
>> - /* Take the minimum kill value. This is the same as
>> OR
>> - * between 2 kill values. If the value is negative,
>> - * the pixel will be killed.
>> - */
>> - val = LLVMBuildLoad(builder, ctx->postponed_kill,
>> "");
>> - val = lp_build_emit_llvm_binary(bld_base,
>> TGSI_OPCODE_MIN,
>> - val,
>> emit_data->args[0]);
>> - LLVMBuildStore(builder, val, ctx->postponed_kill);
>> - } else {
>> - LLVMBuildStore(builder,
>> - LLVMConstReal(ctx->f32, -1),
>> - ctx->postponed_kill);
>> - }
>> + LLVMValueRef val;
>> +
>> + /* Take the minimum kill value. This is the same as OR
>> + * between 2 kill values. If the value is negative,
>> + * the pixel will be killed.
>> + */
>> + val = LLVMBuildLoad(builder, ctx->postponed_kill, "");
>> + val = lp_build_emit_llvm_binary(bld_base, TGSI_OPCODE_MIN,
>> + val, emit_data->args[0]);
>> + LLVMBuildStore(builder, val, ctx->postponed_kill);
>> return;
>> }
>>
>> - if (emit_data->inst->Instruction.Opcode == TGSI_OPCODE_KILL_IF)
>> - ac_build_kill(&ctx->ac, emit_data->args[0]);
>> - else
>> - ac_build_kill(&ctx->ac, NULL);
>> + ac_build_kill(&ctx->ac, emit_data->args[0]);
>> }
>>
>> static void emit_icmp(const struct lp_build_tgsi_action *action,
>> struct lp_build_tgsi_context *bld_base,
>> struct lp_build_emit_data *emit_data)
>> {
>> unsigned pred;
>> struct si_shader_context *ctx = si_shader_context(bld_base);
>>
>> switch (emit_data->inst->Instruction.Opcode) {
>> @@ -804,21 +795,20 @@ void si_shader_context_init_alu(struct
>> lp_build_tgsi_context *bld_base)
>> bld_base->op_actions[TGSI_OPCODE_IMIN].emit = emit_minmax_int;
>> bld_base->op_actions[TGSI_OPCODE_IMSB].emit = emit_imsb;
>> bld_base->op_actions[TGSI_OPCODE_INEG].emit = emit_ineg;
>> bld_base->op_actions[TGSI_OPCODE_ISHR].emit = emit_ishr;
>> bld_base->op_actions[TGSI_OPCODE_ISGE].emit = emit_icmp;
>> bld_base->op_actions[TGSI_OPCODE_ISLT].emit = emit_icmp;
>> bld_base->op_actions[TGSI_OPCODE_ISSG].emit = emit_ssg;
>> bld_base->op_actions[TGSI_OPCODE_I2F].emit = emit_i2f;
>> bld_base->op_actions[TGSI_OPCODE_KILL_IF].fetch_args =
>> kill_if_fetch_args;
>> bld_base->op_actions[TGSI_OPCODE_KILL_IF].emit = kil_emit;
>> - bld_base->op_actions[TGSI_OPCODE_KILL].emit = kil_emit;
>> bld_base->op_actions[TGSI_OPCODE_LDEXP].emit =
>> build_tgsi_intrinsic_nomem;
>> bld_base->op_actions[TGSI_OPCODE_LDEXP].intr_name =
>> "llvm.amdgcn.ldexp.f32";
>> bld_base->op_actions[TGSI_OPCODE_LSB].emit = emit_lsb;
>> bld_base->op_actions[TGSI_OPCODE_LG2].emit =
>> build_tgsi_intrinsic_nomem;
>> bld_base->op_actions[TGSI_OPCODE_LG2].intr_name = "llvm.log2.f32";
>> bld_base->op_actions[TGSI_OPCODE_MAX].emit =
>> build_tgsi_intrinsic_nomem;
>> bld_base->op_actions[TGSI_OPCODE_MAX].intr_name = "llvm.maxnum.f32";
>> bld_base->op_actions[TGSI_OPCODE_MIN].emit =
>> build_tgsi_intrinsic_nomem;
>> bld_base->op_actions[TGSI_OPCODE_MIN].intr_name = "llvm.minnum.f32";
>> bld_base->op_actions[TGSI_OPCODE_MOD].emit = emit_mod;
>> diff --git a/src/gallium/drivers/svga/svga_tgsi_insn.c
>> b/src/gallium/drivers/svga/svga_tgsi_insn.c
>> index be99ad5..77c45f3 100644
>> --- a/src/gallium/drivers/svga/svga_tgsi_insn.c
>> +++ b/src/gallium/drivers/svga/svga_tgsi_insn.c
>> @@ -1382,43 +1382,20 @@ emit_kill_if(struct svga_shader_emitter *emit,
>> * only used XYZ. The MSDN documentation about this is incorrect.
>> */
>> if (!submit_op0( emit, inst_token( SVGA3DOP_TEXKILL ), dst(src0) ))
>> return FALSE;
>>
>> return TRUE;
>> }
>>
>>
>> /**
>> - * Translate/emit unconditional kill instruction (usually found inside
>> - * an IF/ELSE/ENDIF block).
>> - */
>> -static boolean
>> -emit_kill(struct svga_shader_emitter *emit,
>> - const struct tgsi_full_instruction *insn)
>> -{
>> - SVGA3dShaderDestToken temp;
>> - struct src_register one = get_one_immediate(emit);
>> - SVGA3dShaderInstToken inst = inst_token( SVGA3DOP_TEXKILL );
>> -
>> - /* texkill doesn't allow negation on the operand so lets move
>> - * negation of {1} to a temp register */
>> - temp = get_temp( emit );
>> - if (!submit_op1( emit, inst_token( SVGA3DOP_MOV ), temp,
>> - negate( one ) ))
>> - return FALSE;
>> -
>> - return submit_op0( emit, inst, temp );
>> -}
>> -
>> -
>> -/**
>> * Test if r1 and r2 are the same register.
>> */
>> static boolean
>> same_register(struct src_register r1, struct src_register r2)
>> {
>> return (r1.base.num == r2.base.num &&
>> r1.base.type_upper == r2.base.type_upper &&
>> r1.base.type_lower == r2.base.type_lower);
>> }
>>
>> @@ -2896,23 +2873,20 @@ svga_emit_instruction(struct svga_shader_emitter
>> *emit,
>> case TGSI_OPCODE_ENDIF:
>> return emit_endif( emit, insn );
>>
>> case TGSI_OPCODE_BGNLOOP:
>> return emit_bgnloop( emit, insn );
>> case TGSI_OPCODE_ENDLOOP:
>> return emit_endloop( emit, insn );
>> case TGSI_OPCODE_BRK:
>> return emit_brk( emit, insn );
>>
>> - case TGSI_OPCODE_KILL:
>> - return emit_kill( emit, insn );
>> -
>> case TGSI_OPCODE_DST:
>> return emit_dst_insn( emit, insn );
>>
>> case TGSI_OPCODE_LIT:
>> return emit_lit( emit, insn );
>>
>> case TGSI_OPCODE_LRP:
>> return emit_lrp( emit, insn );
>>
>> case TGSI_OPCODE_SSG:
>> @@ -3510,22 +3484,21 @@ needs_to_create_common_immediate(const struct
>> svga_shader_emitter *emit)
>> emit->info.opcode_count[TGSI_OPCODE_DDX] >= 1 ||
>> emit->info.opcode_count[TGSI_OPCODE_DDY] >= 1 ||
>> emit->info.opcode_count[TGSI_OPCODE_ROUND] >= 1 ||
>> emit->info.opcode_count[TGSI_OPCODE_SGE] >= 1 ||
>> emit->info.opcode_count[TGSI_OPCODE_SGT] >= 1 ||
>> emit->info.opcode_count[TGSI_OPCODE_SLE] >= 1 ||
>> emit->info.opcode_count[TGSI_OPCODE_SLT] >= 1 ||
>> emit->info.opcode_count[TGSI_OPCODE_SNE] >= 1 ||
>> emit->info.opcode_count[TGSI_OPCODE_SEQ] >= 1 ||
>> emit->info.opcode_count[TGSI_OPCODE_EXP] >= 1 ||
>> - emit->info.opcode_count[TGSI_OPCODE_LOG] >= 1 ||
>> - emit->info.opcode_count[TGSI_OPCODE_KILL] >= 1)
>> + emit->info.opcode_count[TGSI_OPCODE_LOG] >= 1)
>> return TRUE;
>>
>> return FALSE;
>> }
>>
>>
>> /**
>> * Do we need to create a looping constant?
>> */
>> static boolean
>> diff --git a/src/gallium/drivers/svga/svga_tgsi_vgpu10.c
>> b/src/gallium/drivers/svga/svga_tgsi_vgpu10.c
>> index 5fc93e2..84c7d3b 100644
>> --- a/src/gallium/drivers/svga/svga_tgsi_vgpu10.c
>> +++ b/src/gallium/drivers/svga/svga_tgsi_vgpu10.c
>> @@ -3865,39 +3865,20 @@ emit_kill_if(struct svga_shader_emitter_v10 *emit,
>> emit_src_register(emit, &tmp_src_xxxx);
>> end_emit_instruction(emit);
>>
>> free_temp_indexes(emit);
>>
>> return TRUE;
>> }
>>
>>
>> /**
>> - * Emit code for TGSI_OPCODE_KILL instruction (unconditional discard).
>> - */
>> -static boolean
>> -emit_kill(struct svga_shader_emitter_v10 *emit,
>> - const struct tgsi_full_instruction *inst)
>> -{
>> - struct tgsi_full_src_register zero = make_immediate_reg_float(emit,
>> 0.0f);
>> -
>> - /* DISCARD if 0.0 is zero */
>> - begin_emit_instruction(emit);
>> - emit_discard_opcode(emit, FALSE);
>> - emit_src_register(emit, &zero);
>> - end_emit_instruction(emit);
>> -
>> - return TRUE;
>> -}
>> -
>> -
>> -/**
>> * Emit code for TGSI_OPCODE_LG2 instruction.
>> */
>> static boolean
>> emit_lg2(struct svga_shader_emitter_v10 *emit,
>> const struct tgsi_full_instruction *inst)
>> {
>> /* Note that TGSI_OPCODE_LG2 computes only one value from src.x
>> * while VGPU10 computes four values.
>> *
>> * dst = LG2(src):
>> @@ -5537,22 +5518,20 @@ emit_vgpu10_instruction(struct
>> svga_shader_emitter_v10 *emit,
>> case TGSI_OPCODE_COS:
>> return emit_sincos(emit, inst);
>> case TGSI_OPCODE_DST:
>> return emit_dst(emit, inst);
>> case TGSI_OPCODE_EX2:
>> return emit_ex2(emit, inst);
>> case TGSI_OPCODE_EXP:
>> return emit_exp(emit, inst);
>> case TGSI_OPCODE_IF:
>> return emit_if(emit, inst);
>> - case TGSI_OPCODE_KILL:
>> - return emit_kill(emit, inst);
>> case TGSI_OPCODE_KILL_IF:
>> return emit_kill_if(emit, inst);
>> case TGSI_OPCODE_LG2:
>> return emit_lg2(emit, inst);
>> case TGSI_OPCODE_LIT:
>> return emit_lit(emit, inst);
>> case TGSI_OPCODE_LOG:
>> return emit_log(emit, inst);
>> case TGSI_OPCODE_LRP:
>> return emit_lrp(emit, inst);
>> diff --git a/src/gallium/include/pipe/p_shader_tokens.h
>> b/src/gallium/include/pipe/p_shader_tokens.h
>> index 97deef7..722952d 100644
>> --- a/src/gallium/include/pipe/p_shader_tokens.h
>> +++ b/src/gallium/include/pipe/p_shader_tokens.h
>> @@ -370,21 +370,21 @@ struct tgsi_property_data {
>> #define TGSI_OPCODE_LG2 29
>> #define TGSI_OPCODE_POW 30
>> /* gap */
>> #define TGSI_OPCODE_U2I64 32
>> #define TGSI_OPCODE_CLOCK 33
>> #define TGSI_OPCODE_I2I64 34
>> /* gap */
>> #define TGSI_OPCODE_COS 36
>> #define TGSI_OPCODE_DDX 37
>> #define TGSI_OPCODE_DDY 38
>> -#define TGSI_OPCODE_KILL 39 /* unconditional */
>> +/* gap */
>> #define TGSI_OPCODE_PK2H 40
>> #define TGSI_OPCODE_PK2US 41
>> #define TGSI_OPCODE_PK4B 42
>> #define TGSI_OPCODE_PK4UB 43
>> #define TGSI_OPCODE_D2U64 44
>> #define TGSI_OPCODE_SEQ 45
>> #define TGSI_OPCODE_D2I64 46
>> #define TGSI_OPCODE_SGT 47
>> #define TGSI_OPCODE_SIN 48
>> #define TGSI_OPCODE_SLE 49
>> diff --git a/src/mesa/state_tracker/st_glsl_to_tgsi.cpp
>> b/src/mesa/state_tracker/st_glsl_to_tgsi.cpp
>> index e01268b..5295fac 100644
>> --- a/src/mesa/state_tracker/st_glsl_to_tgsi.cpp
>> +++ b/src/mesa/state_tracker/st_glsl_to_tgsi.cpp
>> @@ -4335,21 +4335,22 @@ glsl_to_tgsi_visitor::visit(ir_discard *ir)
>> st_src_reg temp = get_temp(ir->condition->type);
>> emit_asm(ir, TGSI_OPCODE_AND, st_dst_reg(temp),
>> condition, st_src_reg_for_float(1.0));
>> condition = temp;
>> }
>>
>> condition.negate = ~condition.negate;
>> emit_asm(ir, TGSI_OPCODE_KILL_IF, undef_dst, condition);
>> } else {
>> /* unconditional kil */
>> - emit_asm(ir, TGSI_OPCODE_KILL);
>> + emit_asm(ir, TGSI_OPCODE_KILL_IF, undef_dst,
>> + st_src_reg_for_float(-1.0));
>> }
>> }
>>
>> void
>> glsl_to_tgsi_visitor::visit(ir_if *ir)
>> {
>> unsigned if_opcode;
>> glsl_to_tgsi_instruction *if_inst;
>>
>> ir->condition->accept(this);
>>
>
>
>
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