[Mesa-dev] [PATCH 14/14] radeonsi: increase the maximum UBO size to 2 GB

[Roland Scheidegger]

I'm not quite convinced you can really use huge ubos safely? At least
direct addressing in tgsi can't work (you've only got a 16bit register
index, and it's signed too).

Roland

Am 09.08.2018 um 01:55 schrieb Marek Olšák:
> From: Marek Olšák <marek.olsak at amd.com>
> 
> Same as the closed driver.
> 
> This causes a failure in GL45-CTS.compute_shader.max, which has a trivial
> bug.
> ---
>  src/gallium/drivers/radeonsi/si_get.c | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/src/gallium/drivers/radeonsi/si_get.c b/src/gallium/drivers/radeonsi/si_get.c
> index 41b9cad071b..2852705c806 100644
> --- a/src/gallium/drivers/radeonsi/si_get.c
> +++ b/src/gallium/drivers/radeonsi/si_get.c
> @@ -420,21 +420,21 @@ static int si_get_shader_param(struct pipe_screen* pscreen,
>  	case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS:
>  	case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH:
>  		return 16384;
>  	case PIPE_SHADER_CAP_MAX_INPUTS:
>  		return shader == PIPE_SHADER_VERTEX ? SI_MAX_ATTRIBS : 32;
>  	case PIPE_SHADER_CAP_MAX_OUTPUTS:
>  		return shader == PIPE_SHADER_FRAGMENT ? 8 : 32;
>  	case PIPE_SHADER_CAP_MAX_TEMPS:
>  		return 256; /* Max native temporaries. */
>  	case PIPE_SHADER_CAP_MAX_CONST_BUFFER_SIZE:
> -		return 4096 * sizeof(float[4]); /* actually only memory limits this */
> +		return MIN2(sscreen->info.max_alloc_size, INT_MAX - 3); /* aligned to 4 */
>  	case PIPE_SHADER_CAP_MAX_CONST_BUFFERS:
>  		return SI_NUM_CONST_BUFFERS;
>  	case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS:
>  	case PIPE_SHADER_CAP_MAX_SAMPLER_VIEWS:
>  		return SI_NUM_SAMPLERS;
>  	case PIPE_SHADER_CAP_MAX_SHADER_BUFFERS:
>  		return SI_NUM_SHADER_BUFFERS;
>  	case PIPE_SHADER_CAP_MAX_SHADER_IMAGES:
>  		return SI_NUM_IMAGES;
>  	case PIPE_SHADER_CAP_MAX_UNROLL_ITERATIONS_HINT:
>