[Mesa-dev] [PATCH 5/5] radeonsi: remove chip_class parameter from si_lower_nir
Marek Olšák
maraeo at gmail.com
Wed Mar 7 20:34:39 UTC 2018
From: Marek Olšák <marek.olsak at amd.com>
We can get it from si_screen.
---
src/gallium/drivers/radeonsi/si_compute.c | 3 +--
src/gallium/drivers/radeonsi/si_shader.h | 4 +---
src/gallium/drivers/radeonsi/si_shader_nir.c | 6 +++---
src/gallium/drivers/radeonsi/si_state_shaders.c | 3 +--
4 files changed, 6 insertions(+), 10 deletions(-)
diff --git a/src/gallium/drivers/radeonsi/si_compute.c b/src/gallium/drivers/radeonsi/si_compute.c
index 92d4514..46873cc 100644
--- a/src/gallium/drivers/radeonsi/si_compute.c
+++ b/src/gallium/drivers/radeonsi/si_compute.c
@@ -100,21 +100,21 @@ static void si_create_compute_state_async(void *job, int thread_index)
sel.screen = program->screen;
if (program->ir_type == PIPE_SHADER_IR_TGSI) {
tgsi_scan_shader(program->ir.tgsi, &sel.info);
sel.tokens = program->ir.tgsi;
} else {
assert(program->ir_type == PIPE_SHADER_IR_NIR);
sel.nir = program->ir.nir;
si_nir_scan_shader(sel.nir, &sel.info);
- si_lower_nir(&sel, program->compiler_ctx_state.chip_class);
+ si_lower_nir(&sel);
}
sel.type = PIPE_SHADER_COMPUTE;
sel.local_size = program->local_size;
si_get_active_slot_masks(&sel.info,
&program->active_const_and_shader_buffers,
&program->active_samplers_and_images);
program->shader.selector = &sel;
@@ -179,21 +179,20 @@ static void *si_create_compute_state(
program->ir.tgsi = tgsi_dup_tokens(cso->prog);
if (!program->ir.tgsi) {
FREE(program);
return NULL;
}
} else {
assert(cso->ir_type == PIPE_SHADER_IR_NIR);
program->ir.nir = (struct nir_shader *) cso->prog;
}
- program->compiler_ctx_state.chip_class = sctx->b.chip_class;
program->compiler_ctx_state.debug = sctx->debug;
program->compiler_ctx_state.is_debug_context = sctx->is_debug;
p_atomic_inc(&sscreen->num_shaders_created);
util_queue_fence_init(&program->ready);
struct util_async_debug_callback async_debug;
bool wait =
(sctx->debug.debug_message && !sctx->debug.async) ||
sctx->is_debug ||
si_can_dump_shader(sscreen, PIPE_SHADER_COMPUTE);
diff --git a/src/gallium/drivers/radeonsi/si_shader.h b/src/gallium/drivers/radeonsi/si_shader.h
index 23f9d20..f589789 100644
--- a/src/gallium/drivers/radeonsi/si_shader.h
+++ b/src/gallium/drivers/radeonsi/si_shader.h
@@ -300,22 +300,20 @@ enum {
SI_FIX_FETCH_RGB_8, /* A = 1.0 */
SI_FIX_FETCH_RGB_8_INT, /* A = 1 */
SI_FIX_FETCH_RGB_16,
SI_FIX_FETCH_RGB_16_INT,
};
struct si_shader;
/* State of the context creating the shader object. */
struct si_compiler_ctx_state {
- enum chip_class chip_class;
-
/* Should only be used by si_init_shader_selector_async and
* si_build_shader_variant if thread_index == -1 (non-threaded). */
LLVMTargetMachineRef tm;
/* Used if thread_index == -1 or if debug.async is true. */
struct pipe_debug_callback debug;
/* Used for creating the log string for gallium/ddebug. */
bool is_debug_context;
};
@@ -667,21 +665,21 @@ void si_shader_binary_read_config(struct ac_shader_binary *binary,
struct si_shader_config *conf,
unsigned symbol_offset);
const char *si_get_shader_name(const struct si_shader *shader, unsigned processor);
/* si_shader_nir.c */
void si_nir_scan_shader(const struct nir_shader *nir,
struct tgsi_shader_info *info);
void si_nir_scan_tess_ctrl(const struct nir_shader *nir,
const struct tgsi_shader_info *info,
struct tgsi_tessctrl_info *out);
-void si_lower_nir(struct si_shader_selector *sel, enum chip_class chip_class);
+void si_lower_nir(struct si_shader_selector *sel);
/* Inline helpers. */
/* Return the pointer to the main shader part's pointer. */
static inline struct si_shader **
si_get_main_shader_part(struct si_shader_selector *sel,
struct si_shader_key *key)
{
if (key->as_ls)
return &sel->main_shader_part_ls;
diff --git a/src/gallium/drivers/radeonsi/si_shader_nir.c b/src/gallium/drivers/radeonsi/si_shader_nir.c
index 54ab0af..e537735 100644
--- a/src/gallium/drivers/radeonsi/si_shader_nir.c
+++ b/src/gallium/drivers/radeonsi/si_shader_nir.c
@@ -14,22 +14,22 @@
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
* THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
* DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
* OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
* USE OR OTHER DEALINGS IN THE SOFTWARE.
*/
-#include "si_shader.h"
#include "si_shader_internal.h"
+#include "si_pipe.h"
#include "ac_nir_to_llvm.h"
#include "tgsi/tgsi_from_mesa.h"
#include "compiler/nir/nir.h"
#include "compiler/nir_types.h"
static int
@@ -616,21 +616,21 @@ void si_nir_scan_shader(const struct nir_shader *nir,
nir_foreach_instr(instr, block)
scan_instruction(info, instr);
}
}
/**
* Perform "lowering" operations on the NIR that are run once when the shader
* selector is created.
*/
void
-si_lower_nir(struct si_shader_selector* sel, enum chip_class chip_class)
+si_lower_nir(struct si_shader_selector* sel)
{
/* Adjust the driver location of inputs and outputs. The state tracker
* interprets them as slots, while the ac/nir backend interprets them
* as individual components.
*/
nir_foreach_variable(variable, &sel->nir->inputs)
variable->data.driver_location *= 4;
nir_foreach_variable(variable, &sel->nir->outputs) {
variable->data.driver_location *= 4;
@@ -666,21 +666,21 @@ si_lower_nir(struct si_shader_selector* sel, enum chip_class chip_class)
const nir_lower_subgroups_options subgroups_options = {
.subgroup_size = 64,
.ballot_bit_size = 64,
.lower_to_scalar = true,
.lower_subgroup_masks = true,
.lower_vote_trivial = false,
};
NIR_PASS_V(sel->nir, nir_lower_subgroups, &subgroups_options);
- ac_lower_indirect_derefs(sel->nir, chip_class);
+ ac_lower_indirect_derefs(sel->nir, sel->screen->info.chip_class);
bool progress;
do {
progress = false;
/* (Constant) copy propagation is needed for txf with offsets. */
NIR_PASS(progress, sel->nir, nir_copy_prop);
NIR_PASS(progress, sel->nir, nir_opt_remove_phis);
NIR_PASS(progress, sel->nir, nir_opt_dce);
if (nir_opt_trivial_continues(sel->nir)) {
diff --git a/src/gallium/drivers/radeonsi/si_state_shaders.c b/src/gallium/drivers/radeonsi/si_state_shaders.c
index 8e02a04..8fe4c04 100644
--- a/src/gallium/drivers/radeonsi/si_state_shaders.c
+++ b/src/gallium/drivers/radeonsi/si_state_shaders.c
@@ -1992,21 +1992,21 @@ static void *si_create_shader_selector(struct pipe_context *ctx,
tgsi_scan_shader(state->tokens, &sel->info);
tgsi_scan_tess_ctrl(state->tokens, &sel->info, &sel->tcs_info);
} else {
assert(state->type == PIPE_SHADER_IR_NIR);
sel->nir = state->ir.nir;
si_nir_scan_shader(sel->nir, &sel->info);
si_nir_scan_tess_ctrl(sel->nir, &sel->info, &sel->tcs_info);
- si_lower_nir(sel, sctx->b.chip_class);
+ si_lower_nir(sel);
}
sel->type = sel->info.processor;
p_atomic_inc(&sscreen->num_shaders_created);
si_get_active_slot_masks(&sel->info,
&sel->active_const_and_shader_buffers,
&sel->active_samplers_and_images);
/* Record which streamout buffers are enabled. */
for (i = 0; i < sel->so.num_outputs; i++) {
@@ -3114,21 +3114,20 @@ bool si_update_shaders(struct si_context *sctx)
struct pipe_context *ctx = (struct pipe_context*)sctx;
struct si_compiler_ctx_state compiler_state;
struct si_state_rasterizer *rs = sctx->queued.named.rasterizer;
struct si_shader *old_vs = si_get_vs_state(sctx);
bool old_clip_disable = old_vs ? old_vs->key.opt.clip_disable : false;
struct si_shader *old_ps = sctx->ps_shader.current;
unsigned old_spi_shader_col_format =
old_ps ? old_ps->key.part.ps.epilog.spi_shader_col_format : 0;
int r;
- compiler_state.chip_class = sctx->b.chip_class;
compiler_state.tm = sctx->tm;
compiler_state.debug = sctx->debug;
compiler_state.is_debug_context = sctx->is_debug;
/* Update stages before GS. */
if (sctx->tes_shader.cso) {
if (!sctx->tess_rings) {
si_init_tess_factor_ring(sctx);
if (!sctx->tess_rings)
return false;
--
2.7.4
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