[Mesa-dev] [PATCH 2/3] uac/nir: add get_cache_policy() helper and use it

[Dave Airlie]

On Tue, 30 Oct 2018 at 02:04, Samuel Pitoiset <samuel.pitoiset at gmail.com> wrote:
>
> Signed-off-by: Samuel Pitoiset <samuel.pitoiset at gmail.com>
> ---
>  src/amd/common/ac_nir_to_llvm.c | 38 ++++++++++++++++++++++-----------
>  1 file changed, 26 insertions(+), 12 deletions(-)
>
> diff --git a/src/amd/common/ac_nir_to_llvm.c b/src/amd/common/ac_nir_to_llvm.c
> index e5fbe003f5..736b726beb 100644
> --- a/src/amd/common/ac_nir_to_llvm.c
> +++ b/src/amd/common/ac_nir_to_llvm.c
> @@ -1449,6 +1449,24 @@ static LLVMValueRef extract_vector_range(struct ac_llvm_context *ctx, LLVMValueR
>         }
>  }
>
> +static unsigned get_cache_policy(struct ac_nir_context *ctx,
> +                                enum gl_access_qualifier access,
> +                                bool may_store_unaligned)
> +{
> +       unsigned cache_policy = 0;
> +
> +       /* SI has a TC L1 bug causing corruption of 8bit/16bit stores.  All
> +        * store opcodes not aligned to a dword are affected. The only way to
> +        * get unaligned stores is through shader images.
> +        */
> +       if (((may_store_unaligned && ctx->ac.chip_class == SI) ||
> +            access & (ACCESS_COHERENT | ACCESS_VOLATILE))) {
> +               cache_policy |= ac_glc;
> +       }
> +
> +       return cache_policy;

This comment mentions doing unaligned stores via shader images as a
workaround, the next patch uses this path for shader images, it seems
not entirely clear if it should apply to shader images or not.

Dave.