[Mesa-dev] [PATCH 4/6] radeonsi: remove redundant call to emit_cache_flush in compute clear/copy

Marek Olšák maraeo at gmail.com
Fri Jan 11 23:53:37 UTC 2019


From: Marek Olšák <marek.olsak at amd.com>

launch_grid calls it.
---
 src/gallium/drivers/radeonsi/si_compute_blit.c | 1 -
 1 file changed, 1 deletion(-)

diff --git a/src/gallium/drivers/radeonsi/si_compute_blit.c b/src/gallium/drivers/radeonsi/si_compute_blit.c
index 086793637f0..11da04bed85 100644
--- a/src/gallium/drivers/radeonsi/si_compute_blit.c
+++ b/src/gallium/drivers/radeonsi/si_compute_blit.c
@@ -72,21 +72,20 @@ static void si_compute_do_clear_or_copy(struct si_context *sctx,
 	assert(src_offset % 4 == 0);
 	assert(dst_offset % 4 == 0);
 	assert(size % 4 == 0);
 
 	assert(dst->target != PIPE_BUFFER || dst_offset + size <= dst->width0);
 	assert(!src || src_offset + size <= src->width0);
 
 	sctx->flags |= SI_CONTEXT_PS_PARTIAL_FLUSH |
 		       SI_CONTEXT_CS_PARTIAL_FLUSH |
 		       si_get_flush_flags(sctx, coher, SI_COMPUTE_DST_CACHE_POLICY);
-	si_emit_cache_flush(sctx);
 
 	/* Save states. */
 	void *saved_cs = sctx->cs_shader_state.program;
 	struct pipe_shader_buffer saved_sb[2] = {};
 	si_get_shader_buffers(sctx, PIPE_SHADER_COMPUTE, 0, src ? 2 : 1, saved_sb);
 
 	/* The memory accesses are coalesced, meaning that the 1st instruction writes
 	 * the 1st contiguous block of data for the whole wave, the 2nd instruction
 	 * writes the 2nd contiguous block of data, etc.
 	 */
-- 
2.17.1



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