[Mesa-dev] [PATCH 1/2] radeonsi: merge & rename texture BO metadata functions
Marek Olšák
maraeo at gmail.com
Wed Jan 16 00:10:47 UTC 2019
From: Marek Olšák <marek.olsak at amd.com>
---
src/gallium/drivers/radeonsi/si_texture.c | 117 ++++++++++------------
1 file changed, 53 insertions(+), 64 deletions(-)
diff --git a/src/gallium/drivers/radeonsi/si_texture.c b/src/gallium/drivers/radeonsi/si_texture.c
index c169d4e443d..a56674b6000 100644
--- a/src/gallium/drivers/radeonsi/si_texture.c
+++ b/src/gallium/drivers/radeonsi/si_texture.c
@@ -328,51 +328,25 @@ static int si_init_surface(struct si_screen *sscreen,
((uint64_t)pitch * surface->u.legacy.level[0].nblk_y * bpe) / 4;
}
if (offset) {
for (i = 0; i < ARRAY_SIZE(surface->u.legacy.level); ++i)
surface->u.legacy.level[i].offset += offset;
}
}
return 0;
}
-static void si_texture_init_metadata(struct si_screen *sscreen,
- struct si_texture *tex,
- struct radeon_bo_metadata *metadata)
-{
- struct radeon_surf *surface = &tex->surface;
-
- memset(metadata, 0, sizeof(*metadata));
-
- if (sscreen->info.chip_class >= GFX9) {
- metadata->u.gfx9.swizzle_mode = surface->u.gfx9.surf.swizzle_mode;
- } else {
- metadata->u.legacy.microtile = surface->u.legacy.level[0].mode >= RADEON_SURF_MODE_1D ?
- RADEON_LAYOUT_TILED : RADEON_LAYOUT_LINEAR;
- metadata->u.legacy.macrotile = surface->u.legacy.level[0].mode >= RADEON_SURF_MODE_2D ?
- RADEON_LAYOUT_TILED : RADEON_LAYOUT_LINEAR;
- metadata->u.legacy.pipe_config = surface->u.legacy.pipe_config;
- metadata->u.legacy.bankw = surface->u.legacy.bankw;
- metadata->u.legacy.bankh = surface->u.legacy.bankh;
- metadata->u.legacy.tile_split = surface->u.legacy.tile_split;
- metadata->u.legacy.mtilea = surface->u.legacy.mtilea;
- metadata->u.legacy.num_banks = surface->u.legacy.num_banks;
- metadata->u.legacy.stride = surface->u.legacy.level[0].nblk_x * surface->bpe;
- metadata->u.legacy.scanout = (surface->flags & RADEON_SURF_SCANOUT) != 0;
- }
-}
-
-static void si_surface_import_metadata(struct si_screen *sscreen,
- struct radeon_surf *surf,
- struct radeon_bo_metadata *metadata,
- enum radeon_surf_mode *array_mode,
- bool *is_scanout)
+static void si_get_display_metadata(struct si_screen *sscreen,
+ struct radeon_surf *surf,
+ struct radeon_bo_metadata *metadata,
+ enum radeon_surf_mode *array_mode,
+ bool *is_scanout)
{
if (sscreen->info.chip_class >= GFX9) {
if (metadata->u.gfx9.swizzle_mode > 0)
*array_mode = RADEON_SURF_MODE_2D;
else
*array_mode = RADEON_SURF_MODE_LINEAR_ALIGNED;
*is_scanout = metadata->u.gfx9.swizzle_mode == 0 ||
metadata->u.gfx9.swizzle_mode % 4 == 2;
@@ -622,86 +596,106 @@ static void si_reallocate_texture_inplace(struct si_context *sctx,
si_texture_reference(&new_tex, NULL);
p_atomic_inc(&sctx->screen->dirty_tex_counter);
}
static uint32_t si_get_bo_metadata_word1(struct si_screen *sscreen)
{
return (ATI_VENDOR_ID << 16) | sscreen->info.pci_id;
}
-static void si_query_opaque_metadata(struct si_screen *sscreen,
- struct si_texture *tex,
- struct radeon_bo_metadata *md)
+static void si_set_tex_bo_metadata(struct si_screen *sscreen,
+ struct si_texture *tex)
{
+ struct radeon_surf *surface = &tex->surface;
struct pipe_resource *res = &tex->buffer.b.b;
- static const unsigned char swizzle[] = {
- PIPE_SWIZZLE_X,
- PIPE_SWIZZLE_Y,
- PIPE_SWIZZLE_Z,
- PIPE_SWIZZLE_W
- };
- uint32_t desc[8], i;
- bool is_array = util_texture_is_array(res->target);
+ struct radeon_bo_metadata md;
- if (!sscreen->info.has_bo_metadata)
- return;
+ memset(&md, 0, sizeof(md));
+
+ if (sscreen->info.chip_class >= GFX9) {
+ md.u.gfx9.swizzle_mode = surface->u.gfx9.surf.swizzle_mode;
+ } else {
+ md.u.legacy.microtile = surface->u.legacy.level[0].mode >= RADEON_SURF_MODE_1D ?
+ RADEON_LAYOUT_TILED : RADEON_LAYOUT_LINEAR;
+ md.u.legacy.macrotile = surface->u.legacy.level[0].mode >= RADEON_SURF_MODE_2D ?
+ RADEON_LAYOUT_TILED : RADEON_LAYOUT_LINEAR;
+ md.u.legacy.pipe_config = surface->u.legacy.pipe_config;
+ md.u.legacy.bankw = surface->u.legacy.bankw;
+ md.u.legacy.bankh = surface->u.legacy.bankh;
+ md.u.legacy.tile_split = surface->u.legacy.tile_split;
+ md.u.legacy.mtilea = surface->u.legacy.mtilea;
+ md.u.legacy.num_banks = surface->u.legacy.num_banks;
+ md.u.legacy.stride = surface->u.legacy.level[0].nblk_x * surface->bpe;
+ md.u.legacy.scanout = (surface->flags & RADEON_SURF_SCANOUT) != 0;
+ }
assert(tex->dcc_separate_buffer == NULL);
assert(tex->surface.fmask_size == 0);
/* Metadata image format format version 1:
* [0] = 1 (metadata format identifier)
* [1] = (VENDOR_ID << 16) | PCI_ID
* [2:9] = image descriptor for the whole resource
* [2] is always 0, because the base address is cleared
* [9] is the DCC offset bits [39:8] from the beginning of
* the buffer
* [10:10+LAST_LEVEL] = mipmap level offset bits [39:8] for each level
*/
- md->metadata[0] = 1; /* metadata image format version 1 */
+ md.metadata[0] = 1; /* metadata image format version 1 */
/* TILE_MODE_INDEX is ambiguous without a PCI ID. */
- md->metadata[1] = si_get_bo_metadata_word1(sscreen);
+ md.metadata[1] = si_get_bo_metadata_word1(sscreen);
+
+ static const unsigned char swizzle[] = {
+ PIPE_SWIZZLE_X,
+ PIPE_SWIZZLE_Y,
+ PIPE_SWIZZLE_Z,
+ PIPE_SWIZZLE_W
+ };
+ bool is_array = util_texture_is_array(res->target);
+ uint32_t desc[8];
si_make_texture_descriptor(sscreen, tex, true,
res->target, res->format,
swizzle, 0, res->last_level, 0,
is_array ? res->array_size - 1 : 0,
res->width0, res->height0, res->depth0,
desc, NULL);
si_set_mutable_tex_desc_fields(sscreen, tex, &tex->surface.u.legacy.level[0],
0, 0, tex->surface.blk_w, false, desc);
/* Clear the base address and set the relative DCC offset. */
desc[0] = 0;
desc[1] &= C_008F14_BASE_ADDRESS_HI;
desc[7] = tex->dcc_offset >> 8;
/* Dwords [2:9] contain the image descriptor. */
- memcpy(&md->metadata[2], desc, sizeof(desc));
- md->size_metadata = 10 * 4;
+ memcpy(&md.metadata[2], desc, sizeof(desc));
+ md.size_metadata = 10 * 4;
/* Dwords [10:..] contain the mipmap level offsets. */
if (sscreen->info.chip_class <= VI) {
- for (i = 0; i <= res->last_level; i++)
- md->metadata[10+i] = tex->surface.u.legacy.level[i].offset >> 8;
+ for (unsigned i = 0; i <= res->last_level; i++)
+ md.metadata[10+i] = tex->surface.u.legacy.level[i].offset >> 8;
- md->size_metadata += (1 + res->last_level) * 4;
+ md.size_metadata += (1 + res->last_level) * 4;
}
+
+ sscreen->ws->buffer_set_metadata(tex->buffer.buf, &md);
}
-static void si_apply_opaque_metadata(struct si_screen *sscreen,
- struct si_texture *tex,
- struct radeon_bo_metadata *md)
+static void si_get_opaque_metadata(struct si_screen *sscreen,
+ struct si_texture *tex,
+ struct radeon_bo_metadata *md)
{
uint32_t *desc = &md->metadata[2];
if (sscreen->info.chip_class < VI)
return;
/* Return if DCC is enabled. The texture should be set up with it
* already.
*/
if (md->size_metadata >= 10 * 4 && /* at least 2(header) + 8(desc) dwords */
@@ -721,21 +715,20 @@ static void si_apply_opaque_metadata(struct si_screen *sscreen,
static boolean si_texture_get_handle(struct pipe_screen* screen,
struct pipe_context *ctx,
struct pipe_resource *resource,
struct winsys_handle *whandle,
unsigned usage)
{
struct si_screen *sscreen = (struct si_screen*)screen;
struct si_context *sctx;
struct r600_resource *res = r600_resource(resource);
struct si_texture *tex = (struct si_texture*)resource;
- struct radeon_bo_metadata metadata;
bool update_metadata = false;
unsigned stride, offset, slice_size;
bool flush = false;
ctx = threaded_context_unwrap_sync(ctx);
sctx = (struct si_context*)(ctx ? ctx : sscreen->aux_context);
if (resource->target != PIPE_BUFFER) {
/* This is not supported now, but it might be required for OpenCL
* interop in the future.
@@ -779,26 +772,22 @@ static boolean si_texture_get_handle(struct pipe_screen* screen,
flush = false;
/* Disable CMASK if flush_resource isn't going
* to be called.
*/
if (tex->cmask_buffer)
si_texture_discard_cmask(sscreen, tex);
}
/* Set metadata. */
- if (!res->b.is_shared || update_metadata) {
- si_texture_init_metadata(sscreen, tex, &metadata);
- si_query_opaque_metadata(sscreen, tex, &metadata);
-
- sscreen->ws->buffer_set_metadata(res->buf, &metadata);
- }
+ if (!res->b.is_shared || update_metadata)
+ si_set_tex_bo_metadata(sscreen, tex);
if (sscreen->info.chip_class >= GFX9) {
offset = tex->surface.u.gfx9.surf_offset;
stride = tex->surface.u.gfx9.surf_pitch *
tex->surface.bpe;
slice_size = tex->surface.u.gfx9.surf_slice_size;
} else {
offset = tex->surface.u.legacy.level[0].offset;
stride = tex->surface.u.legacy.level[0].nblk_x *
tex->surface.bpe;
@@ -1418,22 +1407,22 @@ static struct pipe_resource *si_texture_from_winsys_buffer(struct si_screen *ssc
{
enum radeon_surf_mode array_mode;
struct radeon_surf surface = {};
struct radeon_bo_metadata metadata = {};
struct si_texture *tex;
bool is_scanout;
int r;
if (dedicated) {
sscreen->ws->buffer_get_metadata(buf, &metadata);
- si_surface_import_metadata(sscreen, &surface, &metadata,
- &array_mode, &is_scanout);
+ si_get_display_metadata(sscreen, &surface, &metadata,
+ &array_mode, &is_scanout);
} else {
/**
* The bo metadata is unset for un-dedicated images. So we fall
* back to linear. See answer to question 5 of the
* VK_KHX_external_memory spec for some details.
*
* It is possible that this case isn't going to work if the
* surface pitch isn't correctly aligned by default.
*
* In order to support it correctly we require multi-image
@@ -1460,21 +1449,21 @@ static struct pipe_resource *si_texture_from_winsys_buffer(struct si_screen *ssc
if (r)
return NULL;
tex = si_texture_create_object(&sscreen->b, templ, buf, &surface);
if (!tex)
return NULL;
tex->buffer.b.is_shared = true;
tex->buffer.external_usage = usage;
- si_apply_opaque_metadata(sscreen, tex, &metadata);
+ si_get_opaque_metadata(sscreen, tex, &metadata);
assert(tex->surface.tile_swizzle == 0);
return &tex->buffer.b.b;
}
static struct pipe_resource *si_texture_from_handle(struct pipe_screen *screen,
const struct pipe_resource *templ,
struct winsys_handle *whandle,
unsigned usage)
{
--
2.17.1
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