[Mesa-dev] [PATCH 1/2] radv: store a pointer to rad_info in the pipeline

Bas Nieuwenhuizen bas at basnieuwenhuizen.nl
Fri Jul 12 13:53:02 UTC 2019


Please don't introduce multiple ways to do the same thing. (for both
patches in the series).

On Fri, Jul 12, 2019 at 10:39 AM Samuel Pitoiset
<samuel.pitoiset at gmail.com> wrote:
>
> Cleanup.
>
> Signed-off-by: Samuel Pitoiset <samuel.pitoiset at gmail.com>
> ---
>  src/amd/vulkan/radv_pipeline.c | 173 ++++++++++++++++-----------------
>  src/amd/vulkan/radv_private.h  |   2 +
>  2 files changed, 87 insertions(+), 88 deletions(-)
>
> diff --git a/src/amd/vulkan/radv_pipeline.c b/src/amd/vulkan/radv_pipeline.c
> index 9b68650fd36..e81afdd426c 100644
> --- a/src/amd/vulkan/radv_pipeline.c
> +++ b/src/amd/vulkan/radv_pipeline.c
> @@ -178,7 +178,7 @@ radv_pipeline_scratch_init(struct radv_device *device,
>                                                       pipeline->shaders[i]->config.scratch_bytes_per_wave);
>
>                         max_stage_waves = MIN2(max_stage_waves,
> -                                 4 * device->physical_device->rad_info.num_good_compute_units *
> +                                 4 * pipeline->info->num_good_compute_units *
>                                   (256 / pipeline->shaders[i]->config.num_vgprs));
>                         max_waves = MAX2(max_waves, max_stage_waves);
>                 }
> @@ -1092,7 +1092,7 @@ radv_pipeline_init_multisample_state(struct radv_pipeline *pipeline,
>  {
>         const VkPipelineMultisampleStateCreateInfo *vkms = pCreateInfo->pMultisampleState;
>         struct radv_multisample_state *ms = &pipeline->graphics.ms;
> -       unsigned num_tile_pipes = pipeline->device->physical_device->rad_info.num_tile_pipes;
> +       unsigned num_tile_pipes = pipeline->info->num_tile_pipes;
>         bool out_of_order_rast = false;
>         int ps_iter_samples = 1;
>         uint32_t mask = 0xffff;
> @@ -1141,7 +1141,7 @@ radv_pipeline_init_multisample_state(struct radv_pipeline *pipeline,
>                 S_028A4C_MULTI_SHADER_ENGINE_PRIM_DISCARD_ENABLE(1) |
>                 S_028A4C_FORCE_EOV_CNTDWN_ENABLE(1) |
>                 S_028A4C_FORCE_EOV_REZ_ENABLE(1);
> -       ms->pa_sc_mode_cntl_0 = S_028A48_ALTERNATE_RBS_PER_TILE(pipeline->device->physical_device->rad_info.chip_class >= GFX9) |
> +       ms->pa_sc_mode_cntl_0 = S_028A48_ALTERNATE_RBS_PER_TILE(pipeline->info->chip_class >= GFX9) |
>                                 S_028A48_VPORT_SCISSOR_ENABLE(1);
>
>         if (ms->num_samples > 1) {
> @@ -1492,7 +1492,7 @@ calculate_gs_info(const VkGraphicsPipelineCreateInfo *pCreateInfo,
>         struct radv_gs_state gs = {0};
>         struct radv_shader_variant_info *gs_info = &pipeline->shaders[MESA_SHADER_GEOMETRY]->info;
>         struct radv_es_output_info *es_info;
> -       if (pipeline->device->physical_device->rad_info.chip_class >= GFX9)
> +       if (pipeline->info->chip_class >= GFX9)
>                 es_info = radv_pipeline_has_tess(pipeline) ? &gs_info->tes.es_info : &gs_info->vs.es_info;
>         else
>                 es_info = radv_pipeline_has_tess(pipeline) ?
> @@ -1835,15 +1835,14 @@ calculate_ngg_info(const VkGraphicsPipelineCreateInfo *pCreateInfo,
>  static void
>  calculate_gs_ring_sizes(struct radv_pipeline *pipeline, const struct radv_gs_state *gs)
>  {
> -       struct radv_device *device = pipeline->device;
> -       unsigned num_se = device->physical_device->rad_info.max_se;
> +       unsigned num_se = pipeline->info->max_se;
>         unsigned wave_size = 64;
>         unsigned max_gs_waves = 32 * num_se; /* max 32 per SE on GCN */
>         /* On GFX6-GFX7, the value comes from VGT_GS_VERTEX_REUSE = 16.
>          * On GFX8+, the value comes from VGT_VERTEX_REUSE_BLOCK_CNTL = 30 (+2).
>          */
>         unsigned gs_vertex_reuse =
> -               (device->physical_device->rad_info.chip_class >= GFX8 ? 32 : 16) * num_se;
> +               (pipeline->info->chip_class >= GFX8 ? 32 : 16) * num_se;
>         unsigned alignment = 256 * num_se;
>         /* The maximum size is 63.999 MB per SE. */
>         unsigned max_size = ((unsigned)(63.999 * 1024 * 1024) & ~255) * num_se;
> @@ -1862,13 +1861,13 @@ calculate_gs_ring_sizes(struct radv_pipeline *pipeline, const struct radv_gs_sta
>         esgs_ring_size = align(esgs_ring_size, alignment);
>         gsvs_ring_size = align(gsvs_ring_size, alignment);
>
> -       if (pipeline->device->physical_device->rad_info.chip_class <= GFX8)
> +       if (pipeline->info->chip_class <= GFX8)
>                 pipeline->graphics.esgs_ring_size = CLAMP(esgs_ring_size, min_esgs_ring_size, max_size);
>
>         pipeline->graphics.gsvs_ring_size = MIN2(gsvs_ring_size, max_size);
>  }
>
> -static void si_multiwave_lds_size_workaround(struct radv_device *device,
> +static void si_multiwave_lds_size_workaround(struct radv_pipeline *pipeline,
>                                              unsigned *lds_size)
>  {
>         /* If tessellation is all offchip and on-chip GS isn't used, this
> @@ -1880,8 +1879,8 @@ static void si_multiwave_lds_size_workaround(struct radv_device *device,
>          *   Make sure we have at least 4k of LDS in use to avoid the bug.
>          *   It applies to workgroup sizes of more than one wavefront.
>          */
> -       if (device->physical_device->rad_info.family == CHIP_BONAIRE ||
> -           device->physical_device->rad_info.family == CHIP_KABINI)
> +       if (pipeline->info->family == CHIP_BONAIRE ||
> +           pipeline->info->family == CHIP_KABINI)
>                 *lds_size = MAX2(*lds_size, 8);
>  }
>
> @@ -1923,14 +1922,14 @@ calculate_tess_state(struct radv_pipeline *pipeline,
>
>         lds_size = pipeline->shaders[MESA_SHADER_TESS_CTRL]->info.tcs.lds_size;
>
> -       if (pipeline->device->physical_device->rad_info.chip_class >= GFX7) {
> +       if (pipeline->info->chip_class >= GFX7) {
>                 assert(lds_size <= 65536);
>                 lds_size = align(lds_size, 512) / 512;
>         } else {
>                 assert(lds_size <= 32768);
>                 lds_size = align(lds_size, 256) / 256;
>         }
> -       si_multiwave_lds_size_workaround(pipeline->device, &lds_size);
> +       si_multiwave_lds_size_workaround(pipeline, &lds_size);
>
>         tess.lds_size = lds_size;
>
> @@ -1986,8 +1985,8 @@ calculate_tess_state(struct radv_pipeline *pipeline,
>                 topology = V_028B6C_OUTPUT_TRIANGLE_CW;
>
>         if (pipeline->device->has_distributed_tess) {
> -               if (pipeline->device->physical_device->rad_info.family == CHIP_FIJI ||
> -                   pipeline->device->physical_device->rad_info.family >= CHIP_POLARIS10)
> +               if (pipeline->info->family == CHIP_FIJI ||
> +                   pipeline->info->family >= CHIP_POLARIS10)
>                         distribution_mode = V_028B6C_DISTRIBUTION_MODE_TRAPEZOIDS;
>                 else
>                         distribution_mode = V_028B6C_DISTRIBUTION_MODE_DONUTS;
> @@ -2099,13 +2098,13 @@ radv_link_shaders(struct radv_pipeline *pipeline, nir_shader **shaders)
>                 if (progress) {
>                         if (nir_lower_global_vars_to_local(ordered_shaders[i])) {
>                                 ac_lower_indirect_derefs(ordered_shaders[i],
> -                                                        pipeline->device->physical_device->rad_info.chip_class);
> +                                                        pipeline->info->chip_class);
>                         }
>                         radv_optimize_nir(ordered_shaders[i], false, false);
>
>                         if (nir_lower_global_vars_to_local(ordered_shaders[i - 1])) {
>                                 ac_lower_indirect_derefs(ordered_shaders[i - 1],
> -                                                        pipeline->device->physical_device->rad_info.chip_class);
> +                                                        pipeline->info->chip_class);
>                         }
>                         radv_optimize_nir(ordered_shaders[i - 1], false, false);
>                 }
> @@ -2187,8 +2186,8 @@ radv_generate_graphics_pipeline_key(struct radv_pipeline *pipeline,
>                 key.vertex_attribute_offsets[location] = desc->offset;
>                 key.vertex_attribute_strides[location] = radv_get_attrib_stride(input_state, desc->binding);
>
> -               if (pipeline->device->physical_device->rad_info.chip_class <= GFX8 &&
> -                   pipeline->device->physical_device->rad_info.family != CHIP_STONEY) {
> +               if (pipeline->info->chip_class <= GFX8 &&
> +                   pipeline->info->family != CHIP_STONEY) {
>                         VkFormat format = input_state->pVertexAttributeDescriptions[i].format;
>                         uint64_t adjust;
>                         switch(format) {
> @@ -2245,14 +2244,14 @@ radv_generate_graphics_pipeline_key(struct radv_pipeline *pipeline,
>         }
>
>         key.col_format = blend->spi_shader_col_format;
> -       if (pipeline->device->physical_device->rad_info.chip_class < GFX8)
> +       if (pipeline->info->chip_class < GFX8)
>                 radv_pipeline_compute_get_int_clamp(pCreateInfo, &key.is_int8, &key.is_int10);
>
>         return key;
>  }
>
>  static void
> -radv_fill_shader_keys(struct radv_device *device,
> +radv_fill_shader_keys(struct radv_pipeline *pipeline,
>                       struct radv_shader_variant_key *keys,
>                        const struct radv_pipeline_key *key,
>                        nir_shader **nir)
> @@ -2284,7 +2283,7 @@ radv_fill_shader_keys(struct radv_device *device,
>                         keys[MESA_SHADER_VERTEX].vs_common_out.as_es = true;
>         }
>
> -       if (device->physical_device->rad_info.chip_class >= GFX10) {
> +       if (pipeline->info->chip_class >= GFX10) {
>                 if (nir[MESA_SHADER_TESS_CTRL]) {
>                         keys[MESA_SHADER_TESS_EVAL].vs_common_out.as_ngg = true;
>                 } else {
> @@ -2395,7 +2394,7 @@ void radv_create_shaders(struct radv_pipeline *pipeline,
>         struct radv_shader_binary *binaries[MESA_SHADER_STAGES] = {NULL};
>         struct radv_shader_variant_key keys[MESA_SHADER_STAGES] = {{{{{0}}}}};
>         unsigned char hash[20], gs_copy_hash[20];
> -       bool use_ngg = device->physical_device->rad_info.chip_class >= GFX10;
> +       bool use_ngg = pipeline->info->chip_class >= GFX10;
>
>         radv_start_feedback(pipeline_feedback);
>
> @@ -2483,7 +2482,7 @@ void radv_create_shaders(struct radv_pipeline *pipeline,
>                         nir_print_shader(nir[i], stderr);
>         }
>
> -       radv_fill_shader_keys(device, keys, key, nir);
> +       radv_fill_shader_keys(pipeline, keys, key, nir);
>
>         if (nir[MESA_SHADER_FRAGMENT]) {
>                 if (!pipeline->shaders[MESA_SHADER_FRAGMENT]) {
> @@ -2512,7 +2511,7 @@ void radv_create_shaders(struct radv_pipeline *pipeline,
>                         !!pipeline->shaders[MESA_SHADER_FRAGMENT]->info.info.ps.num_input_clips_culls;
>         }
>
> -       if (device->physical_device->rad_info.chip_class >= GFX9 && modules[MESA_SHADER_TESS_CTRL]) {
> +       if (pipeline->info->chip_class >= GFX9 && modules[MESA_SHADER_TESS_CTRL]) {
>                 if (!pipeline->shaders[MESA_SHADER_TESS_CTRL]) {
>                         struct nir_shader *combined_nir[] = {nir[MESA_SHADER_VERTEX], nir[MESA_SHADER_TESS_CTRL]};
>                         struct radv_shader_variant_key key = keys[MESA_SHADER_TESS_CTRL];
> @@ -2531,7 +2530,7 @@ void radv_create_shaders(struct radv_pipeline *pipeline,
>                 keys[MESA_SHADER_TESS_EVAL].tes.tcs_num_outputs = util_last_bit64(pipeline->shaders[MESA_SHADER_TESS_CTRL]->info.info.tcs.outputs_written);
>         }
>
> -       if (device->physical_device->rad_info.chip_class >= GFX9 && modules[MESA_SHADER_GEOMETRY]) {
> +       if (pipeline->info->chip_class >= GFX9 && modules[MESA_SHADER_GEOMETRY]) {
>                 gl_shader_stage pre_stage = modules[MESA_SHADER_TESS_EVAL] ? MESA_SHADER_TESS_EVAL : MESA_SHADER_VERTEX;
>                 if (!pipeline->shaders[MESA_SHADER_GEOMETRY]) {
>                         struct nir_shader *combined_nir[] = {nir[pre_stage], nir[MESA_SHADER_GEOMETRY]};
> @@ -2614,7 +2613,7 @@ void radv_create_shaders(struct radv_pipeline *pipeline,
>
>  static uint32_t
>  radv_pipeline_stage_to_user_data_0(struct radv_pipeline *pipeline,
> -                                  gl_shader_stage stage, enum chip_class chip_class)
> +                                  gl_shader_stage stage)
>  {
>         bool has_gs = radv_pipeline_has_gs(pipeline);
>         bool has_tess = radv_pipeline_has_tess(pipeline);
> @@ -2625,9 +2624,9 @@ radv_pipeline_stage_to_user_data_0(struct radv_pipeline *pipeline,
>                 return R_00B030_SPI_SHADER_USER_DATA_PS_0;
>         case MESA_SHADER_VERTEX:
>                 if (has_tess) {
> -                       if (chip_class >= GFX10) {
> +                       if (pipeline->info->chip_class >= GFX10) {
>                                 return R_00B430_SPI_SHADER_USER_DATA_HS_0;
> -                       } else if (chip_class == GFX9) {
> +                       } else if (pipeline->info->chip_class == GFX9) {
>                                 return R_00B430_SPI_SHADER_USER_DATA_LS_0;
>                         } else {
>                                 return R_00B530_SPI_SHADER_USER_DATA_LS_0;
> @@ -2636,7 +2635,7 @@ radv_pipeline_stage_to_user_data_0(struct radv_pipeline *pipeline,
>                 }
>
>                 if (has_gs) {
> -                       if (chip_class >= GFX10) {
> +                       if (pipeline->info->chip_class >= GFX10) {
>                                 return R_00B230_SPI_SHADER_USER_DATA_GS_0;
>                         } else {
>                                 return R_00B330_SPI_SHADER_USER_DATA_ES_0;
> @@ -2648,16 +2647,16 @@ radv_pipeline_stage_to_user_data_0(struct radv_pipeline *pipeline,
>
>                 return R_00B130_SPI_SHADER_USER_DATA_VS_0;
>         case MESA_SHADER_GEOMETRY:
> -               return chip_class == GFX9 ? R_00B330_SPI_SHADER_USER_DATA_ES_0 :
> +               return pipeline->info->chip_class == GFX9 ? R_00B330_SPI_SHADER_USER_DATA_ES_0 :
>                                             R_00B230_SPI_SHADER_USER_DATA_GS_0;
>         case MESA_SHADER_COMPUTE:
>                 return R_00B900_COMPUTE_USER_DATA_0;
>         case MESA_SHADER_TESS_CTRL:
> -               return chip_class == GFX9 ? R_00B430_SPI_SHADER_USER_DATA_LS_0 :
> +               return pipeline->info->chip_class == GFX9 ? R_00B430_SPI_SHADER_USER_DATA_LS_0 :
>                                             R_00B430_SPI_SHADER_USER_DATA_HS_0;
>         case MESA_SHADER_TESS_EVAL:
>                 if (has_gs) {
> -                       return chip_class >= GFX10 ? R_00B230_SPI_SHADER_USER_DATA_GS_0 :
> +                       return pipeline->info->chip_class >= GFX10 ? R_00B230_SPI_SHADER_USER_DATA_GS_0 :
>                                                      R_00B330_SPI_SHADER_USER_DATA_ES_0;
>                 } else if (has_ngg) {
>                         return R_00B230_SPI_SHADER_USER_DATA_GS_0;
> @@ -2892,9 +2891,9 @@ radv_compute_bin_size(struct radv_pipeline *pipeline, const VkGraphicsPipelineCr
>         VkExtent2D extent = {512, 512};
>
>         unsigned log_num_rb_per_se =
> -           util_logbase2_ceil(pipeline->device->physical_device->rad_info.num_render_backends /
> -                              pipeline->device->physical_device->rad_info.max_se);
> -       unsigned log_num_se = util_logbase2_ceil(pipeline->device->physical_device->rad_info.max_se);
> +           util_logbase2_ceil(pipeline->info->num_render_backends /
> +                              pipeline->info->max_se);
> +       unsigned log_num_se = util_logbase2_ceil(pipeline->info->max_se);
>
>         unsigned total_samples = 1u << G_028BE0_MSAA_NUM_SAMPLES(pipeline->graphics.ms.pa_sc_aa_config);
>         unsigned ps_iter_samples = 1u << G_028804_PS_ITER_SAMPLES(pipeline->graphics.ms.db_eqaa);
> @@ -2950,7 +2949,7 @@ radv_pipeline_generate_binning_state(struct radeon_cmdbuf *ctx_cs,
>                                      struct radv_pipeline *pipeline,
>                                      const VkGraphicsPipelineCreateInfo *pCreateInfo)
>  {
> -       if (pipeline->device->physical_device->rad_info.chip_class < GFX9)
> +       if (pipeline->info->chip_class < GFX9)
>                 return;
>
>         uint32_t pa_sc_binner_cntl_0 =
> @@ -2965,7 +2964,7 @@ radv_pipeline_generate_binning_state(struct radeon_cmdbuf *ctx_cs,
>                 unsigned persistent_states_per_bin; /* allowed range: [1, 32] */
>                 unsigned fpovs_per_batch; /* allowed range: [0, 255], 0 = unlimited */
>
> -               switch (pipeline->device->physical_device->rad_info.family) {
> +               switch (pipeline->info->family) {
>                 case CHIP_VEGA10:
>                 case CHIP_VEGA12:
>                 case CHIP_VEGA20:
> @@ -2999,7 +2998,7 @@ radv_pipeline_generate_binning_state(struct radeon_cmdbuf *ctx_cs,
>         radeon_set_context_reg(ctx_cs, R_028C44_PA_SC_BINNER_CNTL_0,
>                                pa_sc_binner_cntl_0);
>
> -       if (pipeline->device->physical_device->rad_info.chip_class >= GFX10) {
> +       if (pipeline->info->chip_class >= GFX10) {
>                 radeon_set_context_reg(ctx_cs, R_028038_DB_DFSM_CONTROL,
>                                        db_dfsm_control);
>         } else {
> @@ -3226,7 +3225,7 @@ radv_pipeline_generate_multisample_state(struct radeon_cmdbuf *ctx_cs,
>          * if no sample lies on the pixel boundary (-8 sample offset). It's
>          * currently always TRUE because the driver doesn't support 16 samples.
>          */
> -       bool exclusion = pipeline->device->physical_device->rad_info.chip_class >= GFX7;
> +       bool exclusion = pipeline->info->chip_class >= GFX7;
>         radeon_set_context_reg(ctx_cs, R_02882C_PA_SU_PRIM_FILTER_CNTL,
>                                S_02882C_XMAX_RIGHT_EXCLUSION(exclusion) |
>                                S_02882C_YMAX_BOTTOM_EXCLUSION(exclusion));
> @@ -3245,7 +3244,7 @@ radv_pipeline_generate_vgt_gs_mode(struct radeon_cmdbuf *ctx_cs,
>                         pipeline->shaders[MESA_SHADER_GEOMETRY];
>
>                 vgt_gs_mode = ac_vgt_gs_mode(gs->info.gs.vertices_out,
> -                                            pipeline->device->physical_device->rad_info.chip_class);
> +                                            pipeline->info->chip_class);
>         } else if (radv_pipeline_has_ngg(pipeline)) {
>                 const struct radv_shader_variant *vs =
>                         pipeline->shaders[MESA_SHADER_TESS_EVAL] ?
> @@ -3320,7 +3319,7 @@ radv_pipeline_generate_hw_vs(struct radeon_cmdbuf *ctx_cs,
>                                cull_dist_mask << 8 |
>                                clip_dist_mask);
>
> -       if (pipeline->device->physical_device->rad_info.chip_class <= GFX8)
> +       if (pipeline->info->chip_class <= GFX8)
>                 radeon_set_context_reg(ctx_cs, R_028AB4_VGT_REUSE_OFF,
>                                        outinfo->writes_viewport_index);
>  }
> @@ -3353,8 +3352,8 @@ radv_pipeline_generate_hw_ls(struct radeon_cmdbuf *cs,
>         radeon_emit(cs, S_00B524_MEM_BASE(va >> 40));
>
>         rsrc2 |= S_00B52C_LDS_SIZE(tess->lds_size);
> -       if (pipeline->device->physical_device->rad_info.chip_class == GFX7 &&
> -           pipeline->device->physical_device->rad_info.family != CHIP_HAWAII)
> +       if (pipeline->info->chip_class == GFX7 &&
> +           pipeline->info->family != CHIP_HAWAII)
>                 radeon_set_sh_reg(cs, R_00B52C_SPI_SHADER_PGM_RSRC2_LS, rsrc2);
>
>         radeon_set_sh_reg_seq(cs, R_00B528_SPI_SHADER_PGM_RSRC1_LS, 2);
> @@ -3422,8 +3421,8 @@ radv_pipeline_generate_hw_ngg(struct radeon_cmdbuf *ctx_cs,
>                                cull_dist_mask << 8 |
>                                clip_dist_mask);
>
> -       bool vgt_reuse_off = pipeline->device->physical_device->rad_info.family == CHIP_NAVI10 &&
> -                            pipeline->device->physical_device->rad_info.chip_external_rev == 0x1 &&
> +       bool vgt_reuse_off = pipeline->info->family == CHIP_NAVI10 &&
> +                            pipeline->info->chip_external_rev == 0x1 &&
>                              es_type == MESA_SHADER_TESS_EVAL;
>
>         radeon_set_context_reg(ctx_cs, R_028AB4_VGT_REUSE_OFF,
> @@ -3475,16 +3474,16 @@ radv_pipeline_generate_hw_hs(struct radeon_cmdbuf *cs,
>  {
>         uint64_t va = radv_buffer_get_va(shader->bo) + shader->bo_offset;
>
> -       if (pipeline->device->physical_device->rad_info.chip_class >= GFX9) {
> +       if (pipeline->info->chip_class >= GFX9) {
>                 unsigned hs_rsrc2 = shader->config.rsrc2;
>
> -               if (pipeline->device->physical_device->rad_info.chip_class >= GFX10) {
> +               if (pipeline->info->chip_class >= GFX10) {
>                         hs_rsrc2 |= S_00B42C_LDS_SIZE_GFX10(tess->lds_size);
>                 } else {
>                         hs_rsrc2 |= S_00B42C_LDS_SIZE_GFX9(tess->lds_size);
>                 }
>
> -               if (pipeline->device->physical_device->rad_info.chip_class >= GFX10) {
> +               if (pipeline->info->chip_class >= GFX10) {
>                         radeon_set_sh_reg_seq(cs, R_00B520_SPI_SHADER_PGM_LO_LS, 2);
>                         radeon_emit(cs, va >> 8);
>                         radeon_emit(cs, S_00B524_MEM_BASE(va >> 40));
> @@ -3559,7 +3558,7 @@ radv_pipeline_generate_tess_shaders(struct radeon_cmdbuf *ctx_cs,
>         radeon_set_context_reg(ctx_cs, R_028B6C_VGT_TF_PARAM,
>                                tess->tf_param);
>
> -       if (pipeline->device->physical_device->rad_info.chip_class >= GFX7)
> +       if (pipeline->info->chip_class >= GFX7)
>                 radeon_set_context_reg_idx(ctx_cs, R_028B58_VGT_LS_HS_CONFIG, 2,
>                                            tess->ls_hs_config);
>         else
> @@ -3614,8 +3613,8 @@ radv_pipeline_generate_hw_gs(struct radeon_cmdbuf *ctx_cs,
>
>         va = radv_buffer_get_va(gs->bo) + gs->bo_offset;
>
> -       if (pipeline->device->physical_device->rad_info.chip_class >= GFX9) {
> -               if (pipeline->device->physical_device->rad_info.chip_class >= GFX10) {
> +       if (pipeline->info->chip_class >= GFX9) {
> +               if (pipeline->info->chip_class >= GFX10) {
>                         radeon_set_sh_reg_seq(cs, R_00B320_SPI_SHADER_PGM_LO_ES, 2);
>                         radeon_emit(cs, va >> 8);
>                         radeon_emit(cs, S_00B324_MEM_BASE(va >> 40));
> @@ -3768,8 +3767,7 @@ radv_pipeline_generate_ps_inputs(struct radeon_cmdbuf *ctx_cs,
>  }
>
>  static uint32_t
> -radv_compute_db_shader_control(const struct radv_device *device,
> -                              const struct radv_pipeline *pipeline,
> +radv_compute_db_shader_control(const struct radv_pipeline *pipeline,
>                                 const struct radv_shader_variant *ps)
>  {
>         unsigned z_order;
> @@ -3778,8 +3776,8 @@ radv_compute_db_shader_control(const struct radv_device *device,
>         else
>                 z_order = V_02880C_LATE_Z;
>
> -       bool disable_rbplus = device->physical_device->has_rbplus &&
> -                             !device->physical_device->rbplus_allowed;
> +       bool disable_rbplus = pipeline->device->physical_device->has_rbplus &&
> +                             !pipeline->device->physical_device->rbplus_allowed;
>
>         /* It shouldn't be needed to export gl_SampleMask when MSAA is disabled
>          * but this appears to break Project Cars (DXVK). See
> @@ -3817,8 +3815,7 @@ radv_pipeline_generate_fragment_shader(struct radeon_cmdbuf *ctx_cs,
>         radeon_emit(cs, ps->config.rsrc2);
>
>         radeon_set_context_reg(ctx_cs, R_02880C_DB_SHADER_CONTROL,
> -                              radv_compute_db_shader_control(pipeline->device,
> -                                                             pipeline, ps));
> +                              radv_compute_db_shader_control(pipeline, ps));
>
>         radeon_set_context_reg(ctx_cs, R_0286CC_SPI_PS_INPUT_ENA,
>                                ps->config.spi_ps_input_ena);
> @@ -3847,8 +3844,8 @@ static void
>  radv_pipeline_generate_vgt_vertex_reuse(struct radeon_cmdbuf *ctx_cs,
>                                         struct radv_pipeline *pipeline)
>  {
> -       if (pipeline->device->physical_device->rad_info.family < CHIP_POLARIS10 ||
> -           pipeline->device->physical_device->rad_info.chip_class >= GFX10)
> +       if (pipeline->info->family < CHIP_POLARIS10 ||
> +           pipeline->info->chip_class >= GFX10)
>                 return;
>
>         unsigned vtx_reuse_depth = 30;
> @@ -3888,7 +3885,7 @@ radv_compute_vgt_shader_stages_en(const struct radv_pipeline *pipeline)
>                 stages |= S_028B54_VS_EN(V_028B54_VS_STAGE_COPY_SHADER);
>         }
>
> -       if (pipeline->device->physical_device->rad_info.chip_class >= GFX9)
> +       if (pipeline->info->chip_class >= GFX9)
>                 stages |= S_028B54_MAX_PRIMGRP_IN_WAVE(2);
>
>         return stages;
> @@ -3991,7 +3988,7 @@ radv_pipeline_generate_pm4(struct radv_pipeline *pipeline,
>         radv_pipeline_generate_vgt_vertex_reuse(ctx_cs, pipeline);
>         radv_pipeline_generate_binning_state(ctx_cs, pipeline, pCreateInfo);
>
> -       if (pipeline->device->physical_device->rad_info.chip_class >= GFX10 && !radv_pipeline_has_ngg(pipeline))
> +       if (pipeline->info->chip_class >= GFX10 && !radv_pipeline_has_ngg(pipeline))
>                 gfx10_pipeline_generate_ge_cntl(ctx_cs, pipeline, tess, gs);
>
>         radeon_set_context_reg(ctx_cs, R_0286E8_SPI_TMPRING_SIZE,
> @@ -4000,7 +3997,7 @@ radv_pipeline_generate_pm4(struct radv_pipeline *pipeline,
>
>         radeon_set_context_reg(ctx_cs, R_028B54_VGT_SHADER_STAGES_EN, radv_compute_vgt_shader_stages_en(pipeline));
>
> -       if (pipeline->device->physical_device->rad_info.chip_class >= GFX7) {
> +       if (pipeline->info->chip_class >= GFX7) {
>                 radeon_set_uconfig_reg_idx(pipeline->device->physical_device,
>                                            cs, R_030908_VGT_PRIMITIVE_TYPE, 1, prim);
>         } else {
> @@ -4022,7 +4019,6 @@ radv_compute_ia_multi_vgt_param_helpers(struct radv_pipeline *pipeline,
>                                          uint32_t prim)
>  {
>         struct radv_ia_multi_vgt_param_helpers ia_multi_vgt_param = {0};
> -       const struct radv_device *device = pipeline->device;
>
>         if (radv_pipeline_has_tess(pipeline))
>                 ia_multi_vgt_param.primgroup_size = tess->num_patches;
> @@ -4033,22 +4029,22 @@ radv_compute_ia_multi_vgt_param_helpers(struct radv_pipeline *pipeline,
>
>         /* GS requirement. */
>         ia_multi_vgt_param.partial_es_wave = false;
> -       if (radv_pipeline_has_gs(pipeline) && device->physical_device->rad_info.chip_class <= GFX8)
> +       if (radv_pipeline_has_gs(pipeline) && pipeline->info->chip_class <= GFX8)
>                 if (SI_GS_PER_ES / ia_multi_vgt_param.primgroup_size >= pipeline->device->gs_table_depth - 3)
>                         ia_multi_vgt_param.partial_es_wave = true;
>
>         ia_multi_vgt_param.wd_switch_on_eop = false;
> -       if (device->physical_device->rad_info.chip_class >= GFX7) {
> +       if (pipeline->info->chip_class >= GFX7) {
>                 /* WD_SWITCH_ON_EOP has no effect on GPUs with less than
>                  * 4 shader engines. Set 1 to pass the assertion below.
>                  * The other cases are hardware requirements. */
> -               if (device->physical_device->rad_info.max_se < 4 ||
> +               if (pipeline->info->max_se < 4 ||
>                     prim == V_008958_DI_PT_POLYGON ||
>                     prim == V_008958_DI_PT_LINELOOP ||
>                     prim == V_008958_DI_PT_TRIFAN ||
>                     prim == V_008958_DI_PT_TRISTRIP_ADJ ||
>                     (pipeline->graphics.prim_restart_enable &&
> -                    (device->physical_device->rad_info.family < CHIP_POLARIS10 ||
> +                    (pipeline->info->family < CHIP_POLARIS10 ||
>                       (prim != V_008958_DI_PT_POINTLIST &&
>                        prim != V_008958_DI_PT_LINESTRIP))))
>                         ia_multi_vgt_param.wd_switch_on_eop = true;
> @@ -4070,15 +4066,15 @@ radv_compute_ia_multi_vgt_param_helpers(struct radv_pipeline *pipeline,
>         ia_multi_vgt_param.partial_vs_wave = false;
>         if (radv_pipeline_has_tess(pipeline)) {
>                 /* Bug with tessellation and GS on Bonaire and older 2 SE chips. */
> -               if ((device->physical_device->rad_info.family == CHIP_TAHITI ||
> -                    device->physical_device->rad_info.family == CHIP_PITCAIRN ||
> -                    device->physical_device->rad_info.family == CHIP_BONAIRE) &&
> +               if ((pipeline->info->family == CHIP_TAHITI ||
> +                    pipeline->info->family == CHIP_PITCAIRN ||
> +                    pipeline->info->family == CHIP_BONAIRE) &&
>                     radv_pipeline_has_gs(pipeline))
>                         ia_multi_vgt_param.partial_vs_wave = true;
>                 /* Needed for 028B6C_DISTRIBUTION_MODE != 0 */
> -               if (device->has_distributed_tess) {
> +               if (pipeline->device->has_distributed_tess) {
>                         if (radv_pipeline_has_gs(pipeline)) {
> -                               if (device->physical_device->rad_info.chip_class <= GFX8)
> +                               if (pipeline->info->chip_class <= GFX8)
>                                         ia_multi_vgt_param.partial_es_wave = true;
>                         } else {
>                                 ia_multi_vgt_param.partial_vs_wave = true;
> @@ -4107,12 +4103,12 @@ radv_compute_ia_multi_vgt_param_helpers(struct radv_pipeline *pipeline,
>                  *
>                  * Reproducer: https://bugs.freedesktop.org/show_bug.cgi?id=109242
>                  */
> -               if (device->physical_device->rad_info.family == CHIP_TONGA ||
> -                   device->physical_device->rad_info.family == CHIP_FIJI ||
> -                   device->physical_device->rad_info.family == CHIP_POLARIS10 ||
> -                   device->physical_device->rad_info.family == CHIP_POLARIS11 ||
> -                   device->physical_device->rad_info.family == CHIP_POLARIS12 ||
> -                   device->physical_device->rad_info.family == CHIP_VEGAM) {
> +               if (pipeline->info->family == CHIP_TONGA ||
> +                   pipeline->info->family == CHIP_FIJI ||
> +                   pipeline->info->family == CHIP_POLARIS10 ||
> +                   pipeline->info->family == CHIP_POLARIS11 ||
> +                   pipeline->info->family == CHIP_POLARIS12 ||
> +                   pipeline->info->family == CHIP_VEGAM) {
>                         ia_multi_vgt_param.partial_vs_wave = true;
>                 }
>         }
> @@ -4120,9 +4116,9 @@ radv_compute_ia_multi_vgt_param_helpers(struct radv_pipeline *pipeline,
>         ia_multi_vgt_param.base =
>                 S_028AA8_PRIMGROUP_SIZE(ia_multi_vgt_param.primgroup_size - 1) |
>                 /* The following field was moved to VGT_SHADER_STAGES_EN in GFX9. */
> -               S_028AA8_MAX_PRIMGRP_IN_WAVE(device->physical_device->rad_info.chip_class == GFX8 ? 2 : 0) |
> -               S_030960_EN_INST_OPT_BASIC(device->physical_device->rad_info.chip_class >= GFX9) |
> -               S_030960_EN_INST_OPT_ADV(device->physical_device->rad_info.chip_class >= GFX9);
> +               S_028AA8_MAX_PRIMGRP_IN_WAVE(pipeline->info->chip_class == GFX8 ? 2 : 0) |
> +               S_030960_EN_INST_OPT_BASIC(pipeline->info->chip_class >= GFX9) |
> +               S_030960_EN_INST_OPT_ADV(pipeline->info->chip_class >= GFX9);
>
>         return ia_multi_vgt_param;
>  }
> @@ -4189,6 +4185,7 @@ radv_pipeline_init(struct radv_pipeline *pipeline,
>                 has_view_index = true;
>
>         pipeline->device = device;
> +       pipeline->info = &device->physical_device->rad_info;
>         pipeline->layout = radv_pipeline_layout_from_handle(pCreateInfo->layout);
>         assert(pipeline->layout);
>
> @@ -4293,7 +4290,7 @@ radv_pipeline_init(struct radv_pipeline *pipeline,
>         radv_compute_vertex_input_state(pipeline, pCreateInfo);
>
>         for (uint32_t i = 0; i < MESA_SHADER_STAGES; i++)
> -               pipeline->user_data_0[i] = radv_pipeline_stage_to_user_data_0(pipeline, i, device->physical_device->rad_info.chip_class);
> +               pipeline->user_data_0[i] = radv_pipeline_stage_to_user_data_0(pipeline, i);
>
>         struct radv_userdata_info *loc = radv_lookup_user_sgpr(pipeline, MESA_SHADER_VERTEX,
>                                                              AC_UD_VS_BASE_VERTEX_START_INSTANCE);
> @@ -4377,7 +4374,6 @@ static void
>  radv_compute_generate_pm4(struct radv_pipeline *pipeline)
>  {
>         struct radv_shader_variant *compute_shader;
> -       struct radv_device *device = pipeline->device;
>         unsigned compute_resource_limits;
>         unsigned waves_per_threadgroup;
>         uint64_t va;
> @@ -4408,10 +4404,10 @@ radv_compute_generate_pm4(struct radv_pipeline *pipeline)
>         compute_resource_limits =
>                 S_00B854_SIMD_DEST_CNTL(waves_per_threadgroup % 4 == 0);
>
> -       if (device->physical_device->rad_info.chip_class >= GFX7) {
> +       if (pipeline->info->chip_class >= GFX7) {
>                 unsigned num_cu_per_se =
> -                       device->physical_device->rad_info.num_good_compute_units /
> -                       device->physical_device->rad_info.max_se;
> +                       pipeline->info->num_good_compute_units /
> +                       pipeline->info->max_se;
>
>                 /* Force even distribution on all SIMDs in CU if the workgroup
>                  * size is 64. This has shown some good improvements if # of
> @@ -4455,6 +4451,7 @@ static VkResult radv_compute_pipeline_create(
>                 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
>
>         pipeline->device = device;
> +       pipeline->info = &device->physical_device->rad_info;
>         pipeline->layout = radv_pipeline_layout_from_handle(pCreateInfo->layout);
>         assert(pipeline->layout);
>
> @@ -4469,7 +4466,7 @@ static VkResult radv_compute_pipeline_create(
>         pStages[MESA_SHADER_COMPUTE] = &pCreateInfo->stage;
>         radv_create_shaders(pipeline, device, cache, &(struct radv_pipeline_key) {0}, pStages, pCreateInfo->flags, pipeline_feedback, stage_feedbacks);
>
> -       pipeline->user_data_0[MESA_SHADER_COMPUTE] = radv_pipeline_stage_to_user_data_0(pipeline, MESA_SHADER_COMPUTE, device->physical_device->rad_info.chip_class);
> +       pipeline->user_data_0[MESA_SHADER_COMPUTE] = radv_pipeline_stage_to_user_data_0(pipeline, MESA_SHADER_COMPUTE);
>         pipeline->need_indirect_descriptor_sets |= pipeline->shaders[MESA_SHADER_COMPUTE]->info.need_indirect_descriptor_sets;
>         result = radv_pipeline_scratch_init(device, pipeline);
>         if (result != VK_SUCCESS) {
> diff --git a/src/amd/vulkan/radv_private.h b/src/amd/vulkan/radv_private.h
> index f4dd526c89d..64042c7eb52 100644
> --- a/src/amd/vulkan/radv_private.h
> +++ b/src/amd/vulkan/radv_private.h
> @@ -1455,6 +1455,8 @@ struct radv_pipeline {
>         struct radv_device *                          device;
>         struct radv_dynamic_state                     dynamic_state;
>
> +       struct radeon_info                            *info;
> +
>         struct radv_pipeline_layout *                 layout;
>
>         bool                                         need_indirect_descriptor_sets;
> --
> 2.22.0
>
> _______________________________________________
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> mesa-dev at lists.freedesktop.org
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