[Mesa-dev] [PATCH] radv: use correct register setter for ngg hw addr

[Dave Airlie]

From: Dave Airlie <airlied at redhat.com>

this shouldn't matter, but it's good to be correct.
---
 src/amd/vulkan/radv_pipeline.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/amd/vulkan/radv_pipeline.c b/src/amd/vulkan/radv_pipeline.c
index 5cdfe6d24eb..c7660c2900c 100644
--- a/src/amd/vulkan/radv_pipeline.c
+++ b/src/amd/vulkan/radv_pipeline.c
@@ -3408,7 +3408,7 @@ radv_pipeline_generate_hw_ngg(struct radeon_cmdbuf *ctx_cs,
 
 	radeon_set_sh_reg_seq(cs, R_00B320_SPI_SHADER_PGM_LO_ES, 2);
 	radeon_emit(cs, va >> 8);
-	radeon_emit(cs, va >> 40);
+	radeon_emit(cs, S_00B324_MEM_BASE(va >> 40));
 	radeon_set_sh_reg_seq(cs, R_00B228_SPI_SHADER_PGM_RSRC1_GS, 2);
 	radeon_emit(cs, shader->config.rsrc1);
 	radeon_emit(cs, shader->config.rsrc2);
-- 
2.21.0