How well would llvm-pipe run on the"Paralella" chip? <o:p></o:p> <o:p> </o:p> See this kickstarter project below. Looks like it might actually get funded.<o:p></o:p> <a href="http://www.kickstarter.com/projects/adapteva/parallella-a-supercomputer-for-everyone/">http://www.kickstarter.com/projects/adapteva/parallella-a-supercomputer-for-everyone/</a><o:p></o:p> <o:p> </o:p> Ignoring for a moment there is no LLVM backend for this CPU yet, how well does the llvm-pipe architecture map this chip's capability?<o:p></o:p> <o:p> </o:p> It's sort of like a "mobile phone" class low-cost 32-bit RISC version of the Intel MIC.<o:p></o:p> <o:p> </o:p> In short:<o:p></o:p> <o:p> </o:p> - 2 ARM host cores.<o:p></o:p> - 16 compute cores @ 800Mhz (64 on better model)<o:p></o:p> - Small amount of embedded SRAM per compute core.<o:p></o:p> - Each core can issue both one Integer and one FP instruction per cycle. (Including FMA)<o:p></o:p> - Flat 64 entry register file.<o:p></o:p> - All cores on 2D mesh fabric and share one address space.<o:p></o:p> - No SIMD, sadly.<o:p></o:p> <o:p> </o:p> Currently they only have GCC running for this chip, but are looking at LLVM.<o:p></o:p> <o:p> </o:p> Just based on the profile of the typicle Gnome 3 style GUI workload, how well might llvm-pipe run on this chip?<o:p></o:p> <o:p> </o:p> <o:p> </o:p> Thanks!