<div dir="ltr">On 4 February 2013 21:48, Chris Forbes <<a href="mailto:chrisf@ijw.co.nz" target="_blank">chrisf@ijw.co.nz</a>> wrote: <div class="gmail_extra"><div class="gmail_quote"><blockquote class="gmail_quote" style="margin:0 0 0 .8ex;border-left:1px #ccc solid;padding-left:1ex"> On Gen6, lower this to `ld` with lod=0 and an extra sample_index parameter. On Gen7, use `ld2dms`. We don't support CMS yet for multisample textures, so we use MCS=0, which does the right thing for both IMS and UMS surfaces. Note: If we do end up emitting specialized shaders based on the MSAA layout, we can emit a slightly shorter message here in the UMS case. V2: Reworked completely, added support for Gen7. Signed-off-by: Chris Forbes <<a href="mailto:chrisf@ijw.co.nz">chrisf@ijw.co.nz</a>> --- src/mesa/drivers/dri/i965/brw_fs_visitor.cpp | 44 ++++++++++++++++++++++++---- 1 file changed, 38 insertions(+), 6 deletions(-) diff --git a/src/mesa/drivers/dri/i965/brw_fs_visitor.cpp b/src/mesa/drivers/dri/i965/brw_fs_visitor.cpp index d4f6fc9..a3b524c 100644 --- a/src/mesa/drivers/dri/i965/brw_fs_visitor.cpp +++ b/src/mesa/drivers/dri/i965/brw_fs_visitor.cpp @@ -1061,9 +1061,17 @@ fs_visitor::emit_texture_gen5(ir_texture *ir, fs_reg dst, fs_reg coordinate, break; case ir_txf: mlen = header_present + 4 * reg_width; + emit(MOV(fs_reg(MRF, base_mrf + mlen - reg_width, BRW_REGISTER_TYPE_UD), lod)); + inst = emit(SHADER_OPCODE_TXF, dst); + break; + case ir_txf_ms: + mlen = header_present + 4 * reg_width; - emit(MOV(fs_reg(MRF, base_mrf + mlen - reg_width, BRW_REGISTER_TYPE_UD), - lod)); + /* lod */ + emit(MOV(fs_reg(MRF, base_mrf + mlen - reg_width, BRW_REGISTER_TYPE_UD), fs_reg(0))); + /* sample index */ + emit(MOV(fs_reg(MRF, base_mrf + mlen, BRW_REGISTER_TYPE_UD), lod /*sample*/)); </blockquote><div> </div><div>Similar comment to the previous patch: I think this would be a lot clearer if we went ahead and added a "sample" parameter to this function rather than repurpose the "lod" parameter. </div><div> </div><blockquote class="gmail_quote" style="margin:0 0 0 .8ex;border-left:1px #ccc solid;padding-left:1ex"> + mlen += reg_width; inst = emit(SHADER_OPCODE_TXF, dst); break; } @@ -1170,16 +1178,35 @@ fs_visitor::emit_texture_gen7(ir_texture *ir, fs_reg dst, fs_reg coordinate, mlen += reg_width; for (int i = 1; i < ir->coordinate->type->vector_elements; i++) { - emit(ADD(fs_reg(MRF, base_mrf + mlen, BRW_REGISTER_TYPE_D), + emit(ADD(fs_reg(MRF, base_mrf + mlen, BRW_REGISTER_TYPE_D), coordinate, offsets[i])); - coordinate.reg_offset++; - mlen += reg_width; + coordinate.reg_offset++; + mlen += reg_width; </blockquote><div> </div><div>These look like unintentional diffs (perhaps due to whitespace changes). Normally I don't get concerned about whitespace conventions, but in this case it's making it hard to follow the patch. </div><div> </div><blockquote class="gmail_quote" style="margin:0 0 0 .8ex;border-left:1px #ccc solid;padding-left:1ex"> + } + break; + case ir_txf_ms: + emit(MOV(fs_reg(MRF, base_mrf + mlen, BRW_REGISTER_TYPE_UD), lod /*sample_index*/)); + mlen += reg_width; + + /* constant zero MCS; we arrange to never actually have a compressed + * multisample surface here for now. TODO: issue ld_mcs to get this first, + * if we ever support texturing from compressed multisample surfaces */ + emit(MOV(fs_reg(MRF, base_mrf + mlen, BRW_REGISTER_TYPE_UD), fs_reg(0u))); + mlen += reg_width; + + /* there is no offsetting for this message; just copy in the integer + * texture coordinates */ + for (int i=0; i < ir->coordinate->type->vector_elements; i++) { + emit(MOV(fs_reg(MRF, base_mrf + mlen, BRW_REGISTER_TYPE_D), + coordinate)); + coordinate.reg_offset++; + mlen += reg_width; } break; } /* Set up the coordinate (except for cases where it was done above) */ - if (ir->op != ir_txd && ir->op != ir_txs && ir->op != ir_txf) { + if (ir->op != ir_txd && ir->op != ir_txs && ir->op != ir_txf && ir->op != ir_txf_ms) { for (int i = 0; i < ir->coordinate->type->vector_elements; i++) { emit(MOV(fs_reg(MRF, base_mrf + mlen), coordinate)); coordinate.reg_offset++; @@ -1195,6 +1222,7 @@ fs_visitor::emit_texture_gen7(ir_texture *ir, fs_reg dst, fs_reg coordinate, case ir_txl: inst = emit(SHADER_OPCODE_TXL, dst); break; case ir_txd: inst = emit(SHADER_OPCODE_TXD, dst); break; case ir_txf: inst = emit(SHADER_OPCODE_TXF, dst); break; + case ir_txf_ms: inst = emit(SHADER_OPCODE_TXF_MS, dst); break; case ir_txs: inst = emit(SHADER_OPCODE_TXS, dst); break; } inst->base_mrf = base_mrf; @@ -1365,6 +1393,10 @@ fs_visitor::visit(ir_texture *ir) ir->lod_info.lod->accept(this); lod = this->result; break; + case ir_txf_ms: + ir->lod_info.sample_index->accept(this); + lod = this->result; + break; }; /* Writemasking doesn't eliminate channels on SIMD8 texture -- 1.8.1.2 _______________________________________________ mesa-dev mailing list <a href="mailto:mesa-dev@lists.freedesktop.org">mesa-dev@lists.freedesktop.org</a> <a href="http://lists.freedesktop.org/mailman/listinfo/mesa-dev" target="_blank">http://lists.freedesktop.org/mailman/listinfo/mesa-dev</a> </blockquote></div> </div></div>