<div dir="ltr">On 6 February 2013 23:26, Kenneth Graunke <<a href="mailto:kenneth@whitecape.org" target="_blank">kenneth@whitecape.org</a>> wrote: <div class="gmail_extra"><div class="gmail_quote"> <blockquote class="gmail_quote" style="margin:0 0 0 .8ex;border-left:1px #ccc solid;padding-left:1ex">Haswell's "Data Cache" data port is a single unit, but split into two SFIDs to allow for more message types without adding more bits in the message descriptor. Untyped Atomic Operations are now message 0010 in the second data cache data port, rather than 6 in the first. NOTE: This is a candidate for the 9.1 branch. Cc: Eric Anholt <<a href="mailto:eric@anholt.net">eric@anholt.net</a>> Signed-off-by: Kenneth Graunke <<a href="mailto:kenneth@whitecape.org">kenneth@whitecape.org</a>> --- src/mesa/drivers/dri/i965/brw_defines.h | 1 + src/mesa/drivers/dri/i965/brw_eu_emit.c | 10 ++++++---- 2 files changed, 7 insertions(+), 4 deletions(-) diff --git a/src/mesa/drivers/dri/i965/brw_defines.h b/src/mesa/drivers/dri/i965/brw_defines.h index 79cc12f..849d127 100644 --- a/src/mesa/drivers/dri/i965/brw_defines.h +++ b/src/mesa/drivers/dri/i965/brw_defines.h @@ -857,6 +857,7 @@ enum brw_message_target { GEN6_SFID_DATAPORT_CONSTANT_CACHE = 9, GEN7_SFID_DATAPORT_DATA_CACHE = 10, + HSW_SFID_DATAPORT_DATA_CACHE_1 = 12, }; #define GEN7_MESSAGE_TARGET_DP_DATA_CACHE 10 diff --git a/src/mesa/drivers/dri/i965/brw_eu_emit.c b/src/mesa/drivers/dri/i965/brw_eu_emit.c index b34754a..cb58231 100644 --- a/src/mesa/drivers/dri/i965/brw_eu_emit.c +++ b/src/mesa/drivers/dri/i965/brw_eu_emit.c @@ -2539,15 +2539,17 @@ void brw_shader_time_add(struct brw_compile *p, brw_set_src0(p, send, brw_vec1_reg(BRW_MESSAGE_REGISTER_FILE, base_mrf, 0)); + unsigned sfid = GEN7_SFID_DATAPORT_DATA_CACHE; + if (intel->is_haswell) + sfid = HSW_SFID_DATAPORT_DATA_CACHE_1; + bool header_present = false; bool eot = false; uint32_t mlen = 2; /* offset, value */ uint32_t rlen = 0; - brw_set_message_descriptor(p, send, - GEN7_SFID_DATAPORT_DATA_CACHE, - mlen, rlen, header_present, eot); + brw_set_message_descriptor(p, send, sfid, mlen, rlen, header_present, eot); - send->bits3.ud |= 6 << 14; /* untyped atomic op */ + send->bits3.ud |= (intel->is_haswell ? 2 : 6) << 14; /* untyped atomic op */ </blockquote><div> </div><div>Can we put the 2 and 6 in a #define somewhere (and maybe reference the appropriate page in the PRM, at least in the case of IVB)? </div><div> </div><blockquote class="gmail_quote" style="margin:0 0 0 .8ex;border-left:1px #ccc solid;padding-left:1ex"> send->bits3.ud |= 0 << 13; /* no return data */ send->bits3.ud |= 1 << 12; /* SIMD8 mode */ send->bits3.ud |= BRW_AOP_ADD << 8; -- 1.8.1.1 _______________________________________________ mesa-dev mailing list <a href="mailto:mesa-dev@lists.freedesktop.org">mesa-dev@lists.freedesktop.org</a> <a href="http://lists.freedesktop.org/mailman/listinfo/mesa-dev" target="_blank">http://lists.freedesktop.org/mailman/listinfo/mesa-dev</a> </blockquote></div> </div></div>