<div dir="ltr">What about drivers without integer support? The IF instruction should have 2 definitions: one for the drivers which support PIPE_SHADER_CAP_INTEGERS, and the other one for those which don't. Obviously, there is no way to change the behavior of the IF opcode if you only have floats.<br>
<br>Marek<br></div><div class="gmail_extra"><br><br><div class="gmail_quote">On Thu, Apr 11, 2013 at 5:20 AM, Zack Rusin <span dir="ltr"><<a href="mailto:zackr@vmware.com" target="_blank">zackr@vmware.com</a>></span> wrote:<br>
<blockquote class="gmail_quote" style="margin:0 0 0 .8ex;border-left:1px #ccc solid;padding-left:1ex">As implemented in tgsi_exec they both test src operands on the bit<br>
level and don't do floating point comperisons as some thought.<br>
This documents them as such to avoid future confusion and fixes<br>
their implementation in llvmpipe.<br>
<br>
Could gallium driver developers make sure that they're handling<br>
those instrunctions correctly? From my quick glance it seems<br>
to be ok, but I don't know those codebases at all.<br>
<br>
Signed-off-by: Zack Rusin <<a href="mailto:zackr@vmware.com">zackr@vmware.com</a>><br>
---<br>
src/gallium/auxiliary/gallivm/lp_bld_tgsi_soa.c | 10 ++++------<br>
src/gallium/auxiliary/tgsi/tgsi_info.c | 2 ++<br>
src/gallium/docs/source/tgsi.rst | 16 ++++++++++------<br>
3 files changed, 16 insertions(+), 12 deletions(-)<br>
<br>
diff --git a/src/gallium/auxiliary/gallivm/lp_bld_tgsi_soa.c b/src/gallium/auxiliary/gallivm/lp_bld_tgsi_soa.c<br>
index 853de09..8a29635 100644<br>
--- a/src/gallium/auxiliary/gallivm/lp_bld_tgsi_soa.c<br>
+++ b/src/gallium/auxiliary/gallivm/lp_bld_tgsi_soa.c<br>
@@ -2370,12 +2370,9 @@ breakc_emit(<br>
struct lp_build_emit_data * emit_data)<br>
{<br>
struct lp_build_tgsi_soa_context * bld = lp_soa_context(bld_base);<br>
- LLVMBuilderRef builder = bld_base->base.gallivm->builder;<br>
struct lp_build_context *uint_bld = &bld_base->uint_bld;<br>
- LLVMValueRef unsigned_cond =<br>
- LLVMBuildBitCast(builder, emit_data->args[0], uint_bld->vec_type, "");<br>
LLVMValueRef cond = lp_build_cmp(uint_bld, PIPE_FUNC_NOTEQUAL,<br>
- unsigned_cond,<br>
+ emit_data->args[0],<br>
uint_bld->zero);<br>
<br>
lp_exec_break_condition(&bld->exec_mask, cond);<br>
@@ -2389,9 +2386,10 @@ if_emit(<br>
{<br>
LLVMValueRef tmp;<br>
struct lp_build_tgsi_soa_context * bld = lp_soa_context(bld_base);<br>
+ struct lp_build_context *uint_bld = &bld_base->uint_bld;<br>
<br>
- tmp = lp_build_cmp(&bld_base->base, PIPE_FUNC_NOTEQUAL,<br>
- emit_data->args[0], bld->bld_base.base.zero);<br>
+ tmp = lp_build_cmp(uint_bld, PIPE_FUNC_NOTEQUAL,<br>
+ emit_data->args[0], uint_bld->zero);<br>
lp_exec_mask_cond_push(&bld->exec_mask, tmp);<br>
}<br>
<br>
diff --git a/src/gallium/auxiliary/tgsi/tgsi_info.c b/src/gallium/auxiliary/tgsi/tgsi_info.c<br>
index 1fadfec..f488351 100644<br>
--- a/src/gallium/auxiliary/tgsi/tgsi_info.c<br>
+++ b/src/gallium/auxiliary/tgsi/tgsi_info.c<br>
@@ -297,6 +297,8 @@ tgsi_opcode_infer_src_type( uint opcode )<br>
case TGSI_OPCODE_TXF:<br>
case TGSI_OPCODE_SAMPLE_I:<br>
case TGSI_OPCODE_SAMPLE_I_MS:<br>
+ case TGSI_OPCODE_IF:<br>
+ case TGSI_OPCODE_BREAKC:<br>
return TGSI_TYPE_UNSIGNED;<br>
case TGSI_OPCODE_MOD:<br>
case TGSI_OPCODE_I2F:<br>
diff --git a/src/gallium/docs/source/tgsi.rst b/src/gallium/docs/source/tgsi.rst<br>
index 28308cb..e6d97d6 100644<br>
--- a/src/gallium/docs/source/tgsi.rst<br>
+++ b/src/gallium/docs/source/tgsi.rst<br>
@@ -863,10 +863,19 @@ This instruction replicates its result.<br>
<br>
TBD<br>
<br>
+<br>
+.. opcode:: BREAKC - Break Conditional<br>
+<br>
+ Conditionally moves the point of execution to the instruction after the<br>
+ next endloop or endswitch. The instruction must appear within a loop/endloop<br>
+ or switch/endswitch. The 32-bit register supplied by src0 is tested at a<br>
+ bit level (treat it as unsigned).<br>
+<br>
<br>
.. opcode:: IF - If<br>
<br>
- TBD<br>
+ Branch based on logical OR result. The 32-bit register supplied by src0 is<br>
+ tested at a bit level. If any bit is nonzero, it will evaluate to true.<br>
<br>
<br>
.. opcode:: ELSE - Else<br>
@@ -1202,11 +1211,6 @@ XXX wait what<br>
<br>
TBD<br>
<br>
-<br>
-.. opcode:: BREAKC - Break Conditional<br>
-<br>
- TBD<br>
-<br>
.. _doubleopcodes:<br>
<br>
Double ISA<br>
<span class="HOEnZb"><font color="#888888">--<br>
1.7.10.4<br>
<br>
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